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    74LS10 Search Results

    74LS10 Result Highlights (1)

    Part ECAD Model Manufacturer Description Download Buy
    SN74LS109ADR Texas Instruments Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset 16-SOIC 0 to 70 Visit Texas Instruments
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    74LS10 Price and Stock

    Rochester Electronics LLC SN74LS109ADR

    IC FF JK TYPE DUAL 1BIT 16SOIC
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    DigiKey SN74LS109ADR Bulk 30,000 488
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    Rochester Electronics LLC SN74LS107ANSR

    IC FF JK TYPE DUAL 1BIT 14SOP
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    DigiKey SN74LS107ANSR Bulk 30,000 202
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    Rochester Electronics LLC SN74LS109AD

    SN74LS109A DUAL J-K POSITIVE-EDG
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    DigiKey SN74LS109AD Bulk 27,302 362
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    Rochester Electronics LLC SN74LS109AN

    IC FF JK TYPE DUAL 1BIT 16DIP
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    DigiKey SN74LS109AN Tube 23,315 375
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    Vyrian SN74LS109AN 4,454
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    Rochester Electronics LLC SN74LS10N

    IC GATE NAND 3CH 3-INP 14DIP
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    DigiKey SN74LS10N Tube 20,010 758
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    SN74LS10N Bulk 1,759 758
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    Vyrian SN74LS10N 4,060
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    74LS10 Datasheets (30)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    74LS10 Fairchild Semiconductor Triple 3-Input NAND Gate Original PDF
    74LS10 On Semiconductor Triple 3-Input NAND Gate Original PDF
    74LS10 Fairchild Semiconductor Full Line Condensed Catalogue 1977 Scan PDF
    74LS10 Raytheon Positive-NAND Gates, Hex Inverters Scan PDF
    74LS10 Signetics Triple Three-Input NAND / AND Gates Scan PDF
    74LS10 Signetics Triple 3-Input NAND / AND Gates Scan PDF
    74LS10 Signetics Integrated Circuits Catalogue 1978/79 Scan PDF
    74LS107 Fairchild Semiconductor Full Line Condensed Catalogue 1977 Scan PDF
    74LS107 Raytheon Dual J-K Negative-Edge-Triggered Flip-Flops Scan PDF
    74LS107 Signetics Dual J-K Flip-Flop Scan PDF
    74LS107 Signetics Dual J-K Flip-Flop Scan PDF
    74LS107 Signetics Integrated Circuits Catalogue 1978/79 Scan PDF
    74LS107DC Fairchild Semiconductor Dual J-K Flip-Flop Scan PDF
    74LS107FC Fairchild Semiconductor Dual J-K Flip-Flop Scan PDF
    74LS107M Unknown TTL Data Book 1980 Scan PDF
    74LS107PC Fairchild Semiconductor Dual J-K Flip-Flop Scan PDF
    74LS109 Fairchild Semiconductor Full Line Condensed Catalogue 1977 Scan PDF
    74LS109 Raytheon Dual J-K Posilive-Edge-Triggered Flip-Flop Scan PDF
    74LS109 Signetics Integrated Circuits Catalogue 1978/79 Scan PDF
    74LS109A Signetics Dual J-K Positive Edge-Triggered Flip-Flop Scan PDF

    74LS10 Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    ttl 74ls10

    Abstract: truth table NOT gate 74 74LS10 74LS10 truth table 751A-02 SN54-74LS10 74LS10 TTL 3 input nand gate 74LS10
    Text: SN54/74LS10 TRIPLE 3-INPUT NAND GATE TRIPLE 3-INPUT NAND GATE VCC 14 1 LOW POWER SCHOTTKY 13 2 12 11 3 4 10 5 9 6 8 J SUFFIX CERAMIC CASE 632-08 7 14 GND 1 N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN


    Original     		SN54/74LS10 51A-02 SN54LSXXJ SN74LSXXN SN74LSXXD ttl 74ls10 truth table NOT gate 74 74LS10 74LS10 truth table 751A-02 SN54-74LS10 74LS10 TTL 3 input nand gate 74LS10 PDF

    DN74LS10

    Abstract: MA161
    Text: I LS TTL DN74LS Series 74LS10 74LS10 T riple 3 - input P o sitiv e NAND Gates • Description D N 74LS10 contains three 3-input positive isolation NAND gate circuits. ■ Features • • • • Low pow er consum ption P,j = 6mW typical High speed ( tpd = 10ns typical)


    OCR Scan     		DN74LS DN74LS10 DN74LS10 14-pin SO-14D) MA161. MA161 PDF

    DN74LS10

    Abstract: MA161
    Text: LS TTL DN74LS Series 74LS10 74LS10 bio74-LSto T riple 3 - input P o sitiv e NAND Gates • Description D N 74LS10 contains three 3-input positive isolation NAND gate circuits. ■ Features • • • • Low pow er consum ption Pd = 6mW typical High speed ( tpd = 10ns typical)


    OCR Scan     		DN74LS DN74LS10 DN74LS10 14-pin SO-14D) MA161. MA161 PDF

    CI 7474

    Abstract: CI 7473 ci 7476 7474 D latch CI 74LS76 CI 74107 TTL 74ls76 fairchild 9024 ci 74LS74 74ls107
    Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED D55 9020 D60 9024, 54/74109, 54S/74S109, 54LS/74LS109 ui 9 D UJ 5 -=pi (3 J Q 2 — J SD 0 CP Z o (3 11 4 K Ä 0 Co “LT in > _6 12 CP 3 -0 14 K Co ° 7 o-i- CP 13 —c K Cd °


    OCR Scan     		54S/74S109, 54LS/74LS109 54H/74H74, 54S/74S74, 54LS/74LS74 54H/74H73, 54LS/74LS279 93L14 54LS/74LS196 54LS/74LS197 CI 7474 CI 7473 ci 7476 7474 D latch CI 74LS76 CI 74107 TTL 74ls76 fairchild 9024 ci 74LS74 74ls107 PDF

    74LS109PC

    Abstract: No abstract text available
    Text: 109 C O N N E C T IO N D IA G R A M PINOUT A /54S /74S 109 v o4LS/74LS109 DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP D E S C R IP T IO N — The '109 consists of tw o high speed, com pletely indepen­ dent transition clocked J K flip-flops. The clocking operation is independent


    OCR Scan     		o4LS/74LS109 54/74S 54/74LS 74LS109PC PDF

    74LS109A

    Abstract: SN54/74LS109A truth table NOT gate 74
    Text: M M O T O R O L A SN54/74LS109A D E S C R IP T IO N — T h e S N 5 4 L S /7 4 L S 1 0 9 A c o n s is ts of tw o hig h speed c o m p le te ly in d e p e n d e n t tra n s itio n clo cked J K flip -flo p s . T he clo c k in g o p e ra tio n is in d e p e n d e n t o f rise and fa ll tim e s o f th e c lo c k w a v e fo rm . The


    OCR Scan     		SN54LS/74LS109A SN54/74LS109A Inp125 74LS109A SN54/74LS109A truth table NOT gate 74 PDF

    Untitled

    Abstract: No abstract text available
    Text: M M O TO R O LA SN54/74LS109A D E S C R IP T IO N — The S N 5 4 L S /7 4 L S 10 9 A consists o f tw o high speed com pletely independent tra n sitio n clocked JK flip-flops. The clocking operation is independent of rise and fa ll tim es o f th e d o c k w aveform . The


    OCR Scan     		SN54/74LS109A PDF

    74LS10

    Abstract: 74LS10 truth table Motorola 74LS TTL 74ls10 TTL IC 74 74 c 2 n 3 h all gate ic data 74
    Text: MOTOROLA SN54/74LS10 TRIPLE 3-INPUT NAND GATE TR IPLE 3-IN P U T NAND GATE Vcc LOW POWER SCHOTTKY nri rrn nn rm 1101 m in J SUFFIX CE R A M IC C A SE 632-08 LU LU LU LU H LU LU GND N SUFFIX i f P Ï Ï l CASIE 646-0 D SUFFIX soie CASE 751A-02 5 ORDERING INFORMATION


    OCR Scan     		SN54/74LS10 51A-02 SN54/74LS10 74LS10 74LS10 truth table Motorola 74LS TTL 74ls10 TTL IC 74 74 c 2 n 3 h all gate ic data 74 PDF

    74LS107A

    Abstract: No abstract text available
    Text: M MOTOROLA SN54/74LS107A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54/74LS107A is a Dual JK Flip-Flop with individual J, K, Direct Clear and Clock Pulse inputs. Output changes are initiated by the HIGH-to-LOW transition of the clock. A LOW signal on CD input overrides the


    OCR Scan     		SN54/74LS107A SN54/74LS73A 74LS107A PDF

    74LS109

    Abstract: No abstract text available
    Text: LS TTL DN74LS Series 74LS109 D N 7 4 L S 1 0 9 Dual J-K Positive Edge-Triggered Flip-Flops with Set and Reset P-2 • Description DN 74LS109 contains tw o positive-edge triggered J-K flipflop circuits, each w ith independent clock-CP, J, K, and direct-coupled set and reset input terminals.


    OCR Scan     		DN74LS DN74LS109 74LS109 16-pin Zwit-500 MA161 PDF

    Untitled

    Abstract: No abstract text available
    Text: GD54/74LS109A DUAL POSITIVE-EDGE- TRIGGERED J-K FLIP-FLOPS Feature Pin Configuration • Positive Edge-Triggering • Direct Set and reset inputs • J and K inputs • Q and Q outputs Vcc CLR2 J2 K2 C LK 2 PR2 Q2 QS R RRRFI R HR y Description This device contains two independent positiveedge-triggered J-K flip-flops with complementary out­


    OCR Scan     		GD54/74LS109A PDF

    74LS107n

    Abstract: 74107PC IC 74LS107
    Text: 107 CONNECTION DIAGRAM P IN O U T A oft 54/74107 O ' 54LS/74LS107^ n o r D UAL JK FLIP-FLO P With Separate Clears and Clocks Ji ^ DESCRIPTION— T he '107 dual J K master/slave flip-flops have a separate clo ck for each flip-flop. Inputs to the master section are controlled by the


    OCR Scan     		54LS/74LS107^ 54/74LS CLS107) 74LS107n 74107PC IC 74LS107 PDF

    751A-02

    Abstract: TTL 74LS10 3 input nand gate 74LS10 SN54-74LS10
    Text: SN54/74LS10 TRIPLE 3-INPUT NAND GATE TRIPLE 3-INPUT NAND GATE VCC 14 1 LOW POWER SCHOTTKY 13 2 12 11 3 4 10 5 9 6 8 J SUFFIX CERAMIC CASE 632-08 7 14 GND 1 N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN


    Original     		SN54/74LS10 51A-02 SN54LSXXJ SN74LSXXN SN74LSXXD 751A-02 TTL 74LS10 3 input nand gate 74LS10 SN54-74LS10 PDF

    74LS107A

    Abstract: 74LS73A 751A-02 SN54LSXXXJ SN74LSXXXD SN74LSXXXN 74LS73
    Text: SN54/74LS107A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS107A is a Dual JK Flip-Flop with individual J, K, Direct Clear and Clock Pulse inputs. Output changes are initiated by the HIGH-to-LOW transition of the clock. A LOW signal on CD input overrides the


    Original     		SN54/74LS107A 74LS107A 74LS73A 751A-02 SN54LSXXXJ SN74LSXXXD SN74LSXXXN 74LS73 PDF

    Untitled

    Abstract: No abstract text available
    Text: 107 AVG Semiconductors_ DDiT Technical Data 74LS107A DV74ALS107 Dual JK Negative Edge-Triggered Flip-Flop N Suffix Plastic DIP AVG-001Case The 74LS107A is a Dual JK Flip-Flop with individual J, K, Direct Clear and Clock Pulse inputs. Output changes are initialized by the HIGH-toLOW transition of the clock. A LOW signal on Clear input overrides the


    OCR Scan     		DV74LS107A DV74ALS107 AVG-001Case 74LS107A AVG-002 1-800-AVG-SEMI DV74LS107A, LS107A ALS107 PDF

    TTL 74ls74

    Abstract: 74ls74 CI 7473 TTL 7474 7476 JK ttl 7474 14 PIN Jk 7476 7474 PIN DIAGRAM pin diagram 7474 7474 16 PIN
    Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED D55 9020 D60 9024, 54/74109, 54S/74S109, 54LS/74LS109 5 ui 9 D UJ -=pi (3 J Q 2 — J SD 0 CP Z o (3 4 K Ä Co “LT in > </> O a 3 -0 K Co ° I- 3 a. I- 3 O 4-0 Co ? 15 D61 54/7474, 54H/74H74,


    OCR Scan     		54S/74S109, 54LS/74LS109 54H/74H74, 54S/74S74, 54LS/74LS74 54H/74H73, 54H/74H73 54H/74H103 54S/74S113 54LS/74LS113 TTL 74ls74 74ls74 CI 7473 TTL 7474 7476 JK ttl 7474 14 PIN Jk 7476 7474 PIN DIAGRAM pin diagram 7474 7474 16 PIN PDF

    IC 74107

    Abstract: IC 74LS107 74LS107 LS107
    Text: Signelics 74107, LS107 Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION transferred to the slave on the H IG H -toLO W Clock transition. For these devices TYPICAL f MAX TYPICAL SUPPLY CURRENT TOTAL 74107 20MHz 20mA 74LS107 45MHz


    OCR Scan     		LS107 1N916, 1N3064, 500ns 500ns IC 74107 IC 74LS107 74LS107 LS107 PDF

    74LSOO

    Abstract: HD74LS109A
    Text: H D 74LS109A . Dual J-K Positive-edge-triggered Flip-Flops with Preset and Clear IP IN ARRANGEMENT •REC O M M EN D ED OPERATING CONDITIONS S ym bol Item fr o c k C lock fre q u e n c y C lo c k High P u ls e w idth S r'.v lo w “ H " D a ta S e tu p tim e


    OCR Scan     		HD74LS109A. QQ14CI14 DG-14 06max 20-IU8 OG-16 DG-24 74LSOO HD74LS109A PDF

    74LS10 pin configuration

    Abstract: No abstract text available
    Text: GD54/74LS10 TRIPLE 3-INPUT POSITIVE NAND GATES Description Pin Configuration This device contains three independent 3-input NAND gates. It performs the Boolean functions Y = A B C or Y = Â + B + Ü in positive logic. Vcc 1C 1Y 3C 3B 3A 3Y 14 13 12 11 10 9


    OCR Scan     		GD54/74LS10 74LS10 pin configuration PDF

    jk flipflop

    Abstract: DN74LS107 MA161
    Text: I LS TTL DN74LS Series 74LS107 D N 74LS107 Dual J-K Flip-Flops with Reset P-1 • Description 74LS107 contains two negative-edge triggered J-K flip­ flop circuits, each with independent clock-CP, J, K, and direct-coupled reset input terminals. ■ Features


    OCR Scan     		DN74LS DN74LS107 DN74LS107 14-pin SO-14D) MA161. jk flipflop MA161 PDF

    74LS183

    Abstract: 74LS275 74LS97 74LS04 74LS00 74ls series 74LS356 74LS93 74LS396 74LS55
    Text: CM O S/BiCM O S Gate Array • LZ93/LZ95/LZ96/LZ97 Series 74LS Series Macro Cell Libraries LZ93/LZ95/LZ96/LZ97 Series Model No. Model No. Model No. Model No. Model No. Model No. Model No. 74LS00 74LS51 74LS107 74LS158 74LS193 74LS261 74LS364 74LS02 74LS54


    OCR Scan     		LZ93/LZ95/LZ96/LZ97 74LS00 74LS02 74LS04 74LS08 74LS10 74LS11 74LS20 74LS21 74LS183 74LS275 74LS97 74ls series 74LS356 74LS93 74LS396 74LS55 PDF

    SN54/74LS109A

    Abstract: 751B-03 truth table NOT gate 74 74LS109A SN54LSXXXJ SN74LSXXXD SN74LSXXXN 74ls109
    Text: SN54/74LS109A DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54/ 74LS109A consists of two high speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D


    Original     		SN54/74LS109A 74LS109A 751B-03 SN54/74LS109A 751B-03 truth table NOT gate 74 SN54LSXXXJ SN74LSXXXD SN74LSXXXN 74ls109 PDF

    LS 107

    Abstract: 74LS107P
    Text: I NATIONAL SEMICOND { L O G I O 05E D | b S D H E S 107 DDb370G 7^ 5 | t/1-07-07 C O N N E C T IO N D IA G R A M P IN O U T A 54/74107 54LS/74LS107 DUAL JK FLIP-FLOP With Separate Clears and Clocks D E S C R IP T I O N — T he '107 dual J K master/slave flip-flops have a separate


    OCR Scan     		DDb370G 54LS/74LS107 t/1-07-07 D0b37 54/74LS CLS107) //07-3X LS 107 74LS107P PDF

    Untitled

    Abstract: No abstract text available
    Text: I LS TTL DN74LS Series 74LS10 74LS10 Triple 3 - input P ositive NAND Gates • Description D N 74LS10 contains three 3-input positive isolation NAND gate circuits. ■ Features • • • • Low pow er consum ption P^ = 6mW typical High speed ( tpd = 10ns typical)


    OCR Scan     		DN74LS DN74LS10 74LS10 14-pin SO-14D) MA161. PDF