PIN COMPATIBILITY ALLOWS PROTOTYPING WITH COMMERCIAL SX-A FPGAS Search Results

RT54SX72SCQ208

Abstract: rt1280 RT54SX32S-CQ208 RTSX72 RT1020-CQ84B aircraft logic gates RTSX72S RT1425 RT14100 RH1020-CQ84V
Contextual Info: Civilian/Scientific Exploration Actel FPGAs for Space Applications Uncompromising in the Extreme Deep Space I Device Speed Grade Gates Logic Modules Available I/Os DSCC SMD Mars Surveyor RadHard RH1020-CQ84V Std 4,000 547 69 5962F90965 RH1280-CQ172V Std 16,000

RTSX32

Abstract: RT54SX32-CQ208 trd24 RTSX16 54SX A54SX16 A54SX32 RT54SX RT54SX72S Actel PQFP208
Contextual Info: v2.1 SX Family FPGAs RadTolerant and HiRel Features High Density Devices • • • RadTolerant SX Family • • • • • • Tested Total Ionizing Dose TID Survivability Level Radiation Performance to 100 Krads (Si) (ICC Standby Parametric) Devices Available from Tested Pedigreed Lots

208-Pin CQFP

Abstract: Actel PQFP208 RTSX32
Contextual Info: v2.1 SX Family FPGAs RadTolerant and HiRel Features High Density Devices • • • RadTolerant SX Family • • • • • • Tested Total Ionizing Dose TID Survivability Level Radiation Performance to 100 Krads (Si) (ICC Standby Parametric) Devices Available from Tested Pedigreed Lots

CQFP 256 PIN actel

Contextual Info: Pr el i mi nar y v 1. 3 54SX Family FPGAs RadTolerant and HiRel Features • 100% Resource Utilization with 100% Pin Locking RadTolerant 54SX Family • Mixed Voltage Support—3.3V Operation with 5.0V Input Tolerance • Tested Total Ionizing Dose TID Survivability Level

Contextual Info: v 2 .0 54SX Family FPGAs RadTolerant and HiRel Hig h D ens it y De vi ces Fe a t ur es • 16,000 and 32,000 Available Logic Gates Rad To ler ant 54S X Fam i ly • Tested Total Ionizing Dose TID Survivability Level • Up to 228 User I/Os • Radiation Performance to 100Krads (Si) (ICC Standby

RTSX32

Abstract: 54SX A54SX16 A54SX32 RT54SX RT54SX72S RTSX16
Contextual Info: v 2 .0 54SX Family FPGAs RadTolerant and HiRel Hig h D ens it y De vi ces Fe a t ur es • 16,000 and 32,000 Available Logic Gates Rad To ler ant 54S X Fam i ly • Tested Total Ionizing Dose TID Survivability Level • Up to 228 User I/Os • Radiation Performance to 100Krads (Si) (ICC Standby

Contextual Info: v 2 .0 54SX Family FPGAs RadTolerant and HiRel Hig h D ens it y De vi ces Fe a t ur es • 16,000 and 32,000 Available Logic Gates Rad To ler ant 54S X Fam i ly • Tested Total Ionizing Dose TID Survivability Level • Up to 228 User I/Os • Radiation Performance to 100Krads (Si) (ICC Standby

Contextual Info: 54SX Family FPGAs RadTolerant and HiRel Features R a d T ole ran t 54SX Family • • • • • TestedTotal Ionizing Dose TID Survivability Level Devices Avail able from Tested Lots Radiation Performance to 100K Rads Up to 160 MHz On-Chip Performance

Contextual Info: W ie te l Preüminary - m v1 . 2 54SXFamily FPGAs RadTolerant and HiRcl Features • 100%Resource Utilization with 100%Pin Locking R a d T o l e r a n t 5 4 S X F am i l y • Mxed Voltage Support— 3.3VOperation with 5.0VInput

ird8

Abstract: LRD12 54SX32 ic tny 176 TNY 227 TNY 251
Contextual Info: ^ c te l P re lim in a ry v l.1 54SX Family FPGAs RadTolerant and HiRel F e a tu re s R a d T o le r a n t 5 4 S X F a m ily • • • • • Tested Total Ionizing Dose TID Survivability Level Devices Available from Tested Lots Radiation Performance to 100K Rads

Orbit Semiconductor

Abstract: CQFP 208 PIN
Contextual Info: Pr el imin a ry v1 .4 54SX Family FPGAs RadTolerant and HiRel F e at u re s H i g h D e n s i ty D e v i c e s R a d T o l e r a n t 5 4 S X F a m i ly • 16,000 and 32,000 Available Logic Gates • Tested Total Ionizing Dose TID Survivability Level • Up to 225 User I/Os

54SX32

Abstract: TRANSISTOR ASY 28 tIRD12 DSA0036603 CQFP 256 PIN actel CQ25 54SX16
Contextual Info: Preliminary v1.5 54SX Family FPGAs RadTolerant and HiRel Fe a t ur es • Up to 225 User I/Os Rad To ler ant 54S X Fam i ly • Up to 1,080 Dedicated Flip-Flops • Tested Total Ionizing Dose TID Survivability Level E asy L ogi c In teg ra ti on • Radiation Performance to 100Krads (Si) (ICC Standby

Contextual Info: P r e l i m i n a r y v 1 .3 54SXFamily FPGAs RadTolerant and HiRcl Features • 100%Resource Utilization with 100%Pin Locking R a d T o l e r a n t 5 4 S X F am i l y • Mxed Voltage Support— 3.3VOperation with 5.0VInput Tolerance • Tested Total IonizingDose TID Survivability Level

Contextual Info: Preliminary v 1 .2 54SX Family FPGAs RadTolerant and HiRel Features • 100%Resource Utilization with 100%Pin Locking Rad T o lera nt 54SX Family • Mixed Voltage Support— 3.3V Operation with 5.0V Input • TestedTotal Ionizing Dose TID Survivability Level

RTSX32

Abstract: TRANSISTOR ASY 28 54SX A54SX16 A54SX32 RT54SX Cqfp256
Contextual Info: Preliminary v1.5.2 54SX Family FPGAs RadTolerant and HiRel Fe a t ur es • Up to 225 User I/Os Rad To ler ant 54S X Fam i ly • Up to 1,080 Dedicated Flip-Flops • Tested Total Ionizing Dose TID Survivability Level E asy L ogi c In teg ra ti on • Radiation Performance to 100Krads (Si) (ICC Standby

RTSX32

Abstract: 54SX32 034 MEC RTSX16
Contextual Info: Preliminary v1.5.1 54SX Family FPGAs RadTolerant and HiRel Fe a t ur es • Up to 225 User I/Os Rad To ler ant 54S X Fam i ly • Up to 1,080 Dedicated Flip-Flops • Tested Total Ionizing Dose TID Survivability Level E asy L ogi c In teg ra ti on • Radiation Performance to 100Krads (Si) (ICC Standby

RTSX32

Abstract: voter PAR64 REQ64 RT54SX72S RT54SX-S TM1019 Cqfp256
Contextual Info: Advanced v0.2 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 Additional SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate <

RT54SX72S

Abstract: RT54SX-S voter PAR64 REQ64 TM1019 CQFP256
Contextual Info: Advanced v0.2 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 Additional SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate <

TM101

Contextual Info: Advanced v1.2.3 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate < 10–10

Contextual Info: Advanced v1.0.1 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate < 10–10

camera-link to hd-SDI converter

Abstract: Virtex-4QV DS-KIT-FX12MM1-G AES-S6DEV-LX150T-G VHDL code for ADC and DAC SPI with FPGA spartan 3 ADQ0007 XC6SL AES-XLX-V4FX-PCIE100-G SPARTAN-3 XC3S400 based MXS3FK ADS-XLX-SP3-EVL400
Contextual Info: Product Selection Guides Table of Contents February 2010 Virtex Series . 2 Spartan Series . 6

XC3S250E TQ144 STARTER KIT BOARD

Abstract: AES-S6DEV-LX150T-G connector FMC LPC samtec DS-KIT-FX12MM1-G ADS-XLX-SP3-EVL1500 xcf128x SPARTAN-3 XC3S400 SPARTAN-3 XC3S400 pq208 architecture SPARTAN-3 XC3S400 based MXS3FK XQ4VSX55
Contextual Info: Product Selection Guides Table of Contents January 2010 Virtex Series . 2 Spartan Series . 6

PQFP240

Abstract: PQFP208 lattice AMI 602 ZyMOS BGA432 CHIP EXPRESS United Technologies Mostek PQFP160 XILINX Actel PQFP208 l324
Contextual Info: NETRANS PS.QXD A 5/30/00 10:22 AM M E R I Page 1 C A N M I C R O S Y S T E M S , I N C . NETRANS PS.QXD 5/30/00 10:22 AM Page 2 SERIOUS ABOUT CONVERSIONS When We Say We’re The Leader In FPGA-to-ASIC Conversions, We Mean It No one has more experience with FPGA-to-ASIC conversions than

Pin Compatibility Allows Prototyping with Commercial SX-A FPGAs

Abstract: RT54SX72S-CQ256 RTSX32S
Contextual Info: Advanced v 0.1.1 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 Additional SEU Hardened Flip-Flops Eliminate Software TMR Necessity LETth > 40, GEO SEU Rate <