PACE1754 Search Results

Contextual Info: PACE1754/SOS PROCESSOR INTERFACE CIRCUIT PIC CMOS/SOS SPACE PROCESSOR MICROPERIPHERAL FEATURES The PACE1754 (PIC) is a support chip for the PACE1750A/AE Processors. It eliminates the SSI/MSI Logic and external system functions required in typical 1750A implementations.

1f58

Abstract: programmable pipeline microcode memory
Contextual Info: PACE1754/SOS PROCESSOR INTERFACE CIRCUIT PIC CMOS/SOS SPACE PROCESSOR MICROPERIPHERAL FEATURES • The PACE1754 (PIC) Is a support chip for the PACE1750A/AE Processor. It eliminates the SSI/ MSI Logic and external system functions required in typical 1750A implementations.

Contextual Info: PACE1754 SINGLE CHIP, 40MHz CMOS PROCESSOR INTERFACE CIRCUIT PIC 4 -FEATU RES • The PACE1754 (PfC) Is a support chip for the PACE1750A Processor. It eliminates the SSI/ MSI Logic and external system functions required In typical 1750A Implementations.

Contextual Info: PACE1754/SOS PROCESSOR INTERFACE CIRCUIT PIC CMOS/SOS SPACE PROCESSOR MICROPERIPHERAL FEATURES • The PACE1754 (PIC) Is a support chip for the PACE1750A/AE Processor. It eliminates the SSI/ MSI Logic and external system functions required In typical 1750A implementations.

f10 SC4

Contextual Info: PACE1754 SINGLE CHIP, 40MHz CMOS PROCESSOR INTERFACE CIRCUIT PIC ri - — - FEATURES The PACE1754 (PIC) Is a support chip fo r the

P1754

Abstract: G10 SC4 IB435 f10 SC4 IB10 IB16 PACE1753 PACE1754 G10SC4 ior scr
Contextual Info: PACE1754 SINGLE CHIP, 40MHz CMOS PROCESSOR INTERFACE CIRCUIT PIC FEATURES The PACE1754 (PIC) is a support chip for the PACE1750A/AE Processor. It eliminates the SSI/ MSI Logic and external system functions required in typical 1750A implementations. Provides a significant savings in part-count and

Contextual Info: PACE1754 SINGLE CHIP, 40MHz CMOS PROCESSOR INTERFACE CIRCUIT PIC FEATURES The PACE1754 (PIC) is a support chip for the PACE1750A/AE Processor. It eliminates the SSI/ MSI Logic and external system functions required in typical 1750A implementations. Provides a significant savings in part-count and

Combo Driver

Abstract: 1750a 1F41 P150A P1753 PACE1754 P1750A ANP16-001
Contextual Info: APPLICATION NOTE PACE P1754 PIC SYSTEM TEST The PACE1754 PIC chip provides the system designer with a system test which may be run at power-up if enabled. This test is very useful for establishing the functionality of the P1750A/AE CPUs, P1753 COMBO, and the P1754 PIC

pace1750

Abstract: P1754-30QGMB IB10 IB16 PACE1753 PACE1754 P1750A mil-std-1750a
Contextual Info: PACE1754/SOS PROCESSOR INTERFACE CIRCUIT PIC CMOS/SOS SPACE PROCESSOR MICROPERIPHERAL FEATURES The PACE1754 (PIC) is a support chip for the PACE1750A/AE Processors. It eliminates the SSI/MSI Logic and external system functions required in typical 1750A implementations.

Contextual Info: PACE1754 SINGLE CHIP, 40MHz CMOS PROCESSOR INTERFACE CIRCUIT PIC FEATURES • The PACE1754 (PIC) is a support chip for the PACE1750A Processor. It eliminates the SSI/ MSI Logic and external system functions required In typical 1750A Implementations. ■ Provides a significant savings in part-count and

Contextual Info: PACE1753 SINGLE CHIP, 40MHz CMOS MMU/COMBO 4 FEATURES Implements the MIL-STD-1750A Instruction Set Architecture for Memory Management and Protection of up to 1 Megaword. A ll mapping memory 10,240 bfts for both the MMU and BPU functions are Included on the chip.

P1753

Abstract: IB435 pace1750 P-175 IB10 PACE1753 PACE1754 P1753-40QGM
Contextual Info: PACE1753 SINGLE CHIP, 40MHz CMOS MMU/COMBO FEATURES Implements the MIL-STD-1750A Instruction Set Architecture for Memory Management and Protection of up to 1 Megaword. All mapping memory 10,240 bits for both the MMU and BPU functions are included on the chip.

1F42

Abstract: up 5135 50v 200a G10 SC4 A00E pace1750 mil-std-1750a 1f44 ior 5130 f10 SC4 PIC Design
Contextual Info: PACE1752/1754 SINGLE CHIP, 40 MHz CMOS PROCESSOR INTERFACE CIRCUIT PIC IP IB IIL O IM IO N IA H V FEATURES • The RftCE1752/1754 (PIC) is a support chip for the RACE1750A Processor. It eliminates the SSI/MSI Logic and external system functions required in

diode sk 4f1/ 02

Abstract: diode sk 4f1 pace1750 pace1750a F9450 diode sk 4f1/ 10 PACE1750AE P1750A MJ015 mil-std-1750a
Contextual Info: PACE1750AE SINGLE CHIP, 40MHz, ENHANCED CMOS 16-BIT PROCESSOR IP 1 F 8 E L M D IN M Y FEATURES — Parametric Memory Inner-Dot Products for Matrix Computations Up To 64K. — Fast Polynomial expansion algorithm. — Fast context switching with instruction to block

pace1750

Abstract: 11 ak 30 a4 edc5 P1753 IB10 PACE1753 PACE1754
Contextual Info: PERFORMANCE SEMICON DU CT OR 50E I • VObEST? DGDlb^G 34>4 * P S C PACE1753 SINGLE CHIP, 40MHz CMOS MMU/COMBO * r - FEATURES ■ — Illegal address error detection— program m able

Contextual Info: pApci7cq SINGLE CHIP, 40MHz CMOS MMU/COMBO FEATURES — Illegal address error detection— programmable — Multi-Master arbitration • Implements the MlL-STD-1750A Instruction Set Architecture for Memory Management and Protection of up to 1 Megaword. All mapping

Contextual Info: PACE1752/1754 SINGLE CHIP, 40 MHz CMOS PROCESSOR INTERFACE CIRCUIT PIC X?- FEATURES • The RACE1752/1754 (PIC) is a support chip for the PACE1750A Processor. It eliminates the SSI/MSI

Contextual Info: PACE 1757M/ME COMPLETE EMBEDDED CPU SUBSYSTEM 4 -FFATURES Implements complete MIL-STD-1750A ISA Including optional MMU, MFSR, and BPU functions. • Programmable address wait states. • Sixteen levels of interrupts are provided per MIL-STD1750A. Interrupts can be either edge- or level-sensitive

Contextual Info: PACE1750AE SINGLE CHIP, 40MHz, ENHANCED CMOS 16-BIT PROCESSOR FEATURES — Parametric Memory Inner-Dot Products for Matrix Computations Up To 64K. — Fast Polynomial expansion algorithm. — Fast context switching with instruction to block move up to 16 new mapping memory page

HIT 7070

Abstract: k1757
Contextual Info: PERFORMANCE SEMI CONDUCTOR SOE D • 70bBST7 000175b 32T ip PACE 1757M/ME PREÜMl COMPLETE EMBEDDED CPU SUBSYSTEM FEATURES Programmable address wait states. Implements complete MIL-STD-1750A ISA Including optional MMU, MFSR, and BPU functions. Sixteen levels of interrupts are provided per MIL-STD1750A. Interrupts can be either edge- or level-sensitive.

5962-8864

Contextual Info: PACE1753 SINGLE CHIP, 40MHz CMOS MMU/COMBO FEATURES • ■ implements the MIL-STD-1750A Instruction Set Architecture for Memory Management and Protection of up to 1 Megaword. All mapping memory 10,240 bits for both the MMU and BPU functions are Included on the chip.

Contextual Info: PACE1753 SINGLE CHIP, 40MHz CMOS MMU/COMBO FEATURES Implements the MIL-STD-1750A Instruction Set Architecture for Memory Management and Protection of up to 1 Megaword. All mapping memory 10,240 bits for both the MMU and BPU functions are included on the chip.

Mem 5116

Abstract: D100D 9F59 1F50 pace1750 PIC dmx example codes P4C168 P4C187 PACE1750A PACE1754
Contextual Info: PERFORMANCE SEMI CONDUCTOR 20E D 70^25=17 PACE1751/1753 SINGLE CHIP, 40 MHz CMOS MMU/COMBO GQ00i7b b • C ^ ilL Q M iM M Y T - 5*3. FEATURES ■ Implements the MIL-STD-1750A Instruction Set Architecture for Memory Management and Protection of up to 1 Megawords. All mapping

DME 40

Abstract: 1F42 8410 psc ft6t 102 scr FIR 3d pace1750 mil-std-1750a pin out of scr BT 106 pic 636 WAOI
Contextual Info: PERFORMANCE SEMICONDUCTOR SDE D • TDbEST? 000172b 32T H P S C PACE 1757M/ME p r e l im in a r y COMPLETE EMBEDDED CPU SUBSYSTEM FEATURES Programmable address wait states. Implements complete M1L-STD-1750A ISA Including optional MMU, MFSR, and BPU functions.