A12L
Abstract: A14L IDT70V3579 IDT70V3579S
Text: HIGH-SPEED 3.3V 32K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access Commercial: 5/6ns max. Pipelined output mode
|
Original
|
PDF
|
IDT70V3579S
100MHz
70V3579
36-Bit)
A12L
A14L
IDT70V3579
IDT70V3579S
|
70V3569
Abstract: A12L A13L IDT70V3569 IDT70V3569S
Text: HIGH-SPEED 3.3V 16K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE PRELIMINARY IDT70V3569S Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed clock to data access
|
Original
|
PDF
|
IDT70V3569S
133MHz
133MHz
wri12/99:
133MHz,
70V3569
A12L
A13L
IDT70V3569
IDT70V3569S
|
Dynachip
Abstract: SR flip flop using discrete gates T flip flop pin configuration DL-5000 i33b DL5000 DL5064 DL5256 DL5528 MUX24
Text: DL5000 Family Fast Field Programmable Gate Array Features • Fast Field Programmable Gate Arrays™ Patented Active Repeater™ Architecture Data and Clock Rates up to 270 MHz Complex operations up to 200 MHz Input Block Register Setup Time 800 ps Output Block Register Clock-to-out 1.6 ns
|
Original
|
PDF
|
DL5000TM
100KH
DL5000
DL5000,
Dynachip
SR flip flop using discrete gates
T flip flop pin configuration
DL-5000
i33b
DL5064
DL5256
DL5528
MUX24
|
tdc 310
Abstract: ba6l BA6R 10 35L U1
Text: HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ 256K x 36 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 4K x 36 banks – 9 megabits of memory on chip
|
Original
|
PDF
|
200MHz
166MHz
133MHz)
14Gbps
SMEN-01-04
BF-208
tdc 310
ba6l
BA6R
10 35L U1
|
ba6l
Abstract: No abstract text available
Text: HIGH-SPEED 3.3V 64K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ 64K x 36 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 1K x 36 banks – 2 megabits of memory on chip
|
Original
|
PDF
|
200MHz
166MHz
133MHz)
14Gbps
SMEN-01-05
SMEN-01-04
ba6l
|
IDT70T659
Abstract: No abstract text available
Text: HIGH-SPEED 2.5V 256/128K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE Features ◆ ◆ ◆ ◆ ◆ ◆ Busy and Interrupt Flags On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port
|
Original
|
PDF
|
256/128K
100mV)
150mV
256-ball
208-pin
208-ball
IDT70T659
|
10 35L U4
Abstract: 70V7589 IDT70V7589 IDT70V7589S BA5L
Text: HIGH-SPEED 3.3V 64K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE PRELIMINARY IDT70V7589S Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ 64K x 36 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 1K x 36 banks
|
Original
|
PDF
|
IDT70V7589S
166MHz
133MHz)
12Gbps
SMEN-01-05
SMEN-01-04
10 35L U4
70V7589
IDT70V7589
IDT70V7589S
BA5L
|
IDT70T659
Abstract: 9S12 CAN 9S12
Text: Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ IDT70T651/9S HIGH-SPEED 2.5V 256/128K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE ◆ On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port
|
Original
|
PDF
|
IDT70T651/9S
256/128K
100mV)
150mV
256-ball
208-pin
208-ball
IDT70T659
9S12 CAN
9S12
|
70V7519
Abstract: IDT70V7519 IDT70V7519S ba6l
Text: HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ 256K x 36 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 4K x 36 banks – 9 megabits of memory on chip
|
Original
|
PDF
|
200MHz
166MHz
133MHz)
14Gbps
BC-256
70V7519
IDT70V7519
IDT70V7519S
ba6l
|
A17R-A0R
Abstract: A17L-A0L 7144
Text: HIGH-SPEED 1.8V 256/128K x 36 IDT70P3519/99 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V/2.5V/1.8V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location Low Power High-speed data access
|
Original
|
PDF
|
256/128K
IDT70P3519/99
200MHz
166MHz)
14Gbps
200MHz
5T2010
5T9010
A17R-A0R
A17L-A0L
7144
|
O23R
Abstract: o32l 70V3579 A12L A14L IDT70V3579 IDT70V3579S optl p2 3.5mm
Text: HIGH-SPEED 3.3V 32K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE IDT70V3579S Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed clock to data access
|
Original
|
PDF
|
IDT70V3579S
133MHz
133MHz
O23R
o32l
70V3579
A12L
A14L
IDT70V3579
IDT70V3579S
optl
p2 3.5mm
|
IDT70T3589
Abstract: IDT70T3599 70T359 70T3589
Text: HIGH-SPEED 2.5V 256/128/64K x 36 IDT70T3519/99/89S SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed data access
|
Original
|
PDF
|
256/128/64K
IDT70T3519/99/89S
200MHz
166MHz
133MHz)
14Gbps
IDT70T3589
IDT70T3599
70T359
70T3589
|
70T3589
Abstract: No abstract text available
Text: HIGH-SPEED 2.5V 256/128/64K x 36 IDT70T3519/99/89S SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed data access
|
Original
|
PDF
|
256/128/64K
IDT70T3519/99/89S
200MHz
166MHz
133MHz)
14Gbps
70T3589
|
Untitled
Abstract: No abstract text available
Text: Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ IDT70T651/9S HIGH-SPEED 2.5V 256/128K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE ◆ On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port
|
Original
|
PDF
|
IDT70T651/9S
256/128K
100mV)
150mV
256-ball
208-pin
208-ball
|
|
IDT70T659
Abstract: No abstract text available
Text: HIGH-SPEED 2.5V 256/128K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed access – Commercial: 10/12/15ns max.
|
Original
|
PDF
|
256/128K
10/12/15ns
IDT70T651/9
IDT70T651/9S
208-ball
BF-208)
70T651
70T659
IDT70T659
|
IDT70T3589
Abstract: IDT70T3599 70T3589
Text: HIGH-SPEED 2.5V PRELIMINARY 256/128/64K x 36 IDT70T3519/99/89S SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed data access
|
Original
|
PDF
|
256/128/64K
IDT70T3519/99/89S
200MHz
166MHz
133MHz)
14Gbps
IDT70T3589
IDT70T3599
70T3589
|
CY7C09569V
Abstract: No abstract text available
Text: CY7C09569V CY7C09579V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3 V 16 K / 32 K x 36 FLEx36 Synchronous Dual-Port Static RAM CY7C09569V CY7C09579V ® 3.3 V 16 K / 32 K × 36 FLEx36 Synchronous Dual-Port Static RAM 3.3 V 16 K / 32 K × 36 FLEx36® Synchronous Dual-Port Static RAM
|
Original
|
PDF
|
CY7C09569V
CY7C09579V
CY7C09289V
CY7C09369V
CY7C09379V
CY7C09389V3
FLEx36®
FLEx36
|
256-pin BGA drawing
Abstract: No abstract text available
Text: HIGH-SPEED 3.3V 32K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 4.2/5/6ns max.
|
Original
|
PDF
|
IDT70V3579S
133MHz
133MHz
256-pin BGA drawing
|
O20R
Abstract: QX 78 O23R w 5667 O28R O25R O20L
Text: HIGH-SPEED 3.3V 16K x 36 SYNCHRONOUS FLOW-THROUGH DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE IDT70V356S Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed clock to data access
|
Original
|
PDF
|
IDT70V356S
150mV)
150mce
208-pin
BF-208)
DR-208)
256-pin
BC-256)
70V356
O20R
QX 78
O23R
w 5667
O28R
O25R
O20L
|
Untitled
Abstract: No abstract text available
Text: HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ 128K x 36 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 2K x 36 banks – 4 megabits of memory on chip
|
Original
|
PDF
|
IDT70V7599S
200MHz
166MHz
133MHz)
14Gbps
BC-256
|
70T3539M
Abstract: No abstract text available
Text: HIGH-SPEED 2.5V 512K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed data access – Commercial: 3.6ns 166MHz /4.2ns (133MHz)(max.)
|
Original
|
PDF
|
IDT70T3539M
166MHz
133MHz)
12Gbps
166MHz
256-pin
BC-256)
70T3539M
|
Untitled
Abstract: No abstract text available
Text: HIGH-SPEED 2.5V 1024K x 36 IDT70T3509M SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed data access – Commercial: 4.2ns 133MHz (max.)
|
Original
|
PDF
|
1024K
IDT70T3509M
133MHz)
133MHz
133MHz
BP-256
BC-256
|
70V3569S6
Abstract: No abstract text available
Text: HIGH-SPEED 3.3V 16K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE IDT70V3569S Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed clock to data access
|
Original
|
PDF
|
IDT70V3569S
133MHz
133MHz
70V3569S6
|
Untitled
Abstract: No abstract text available
Text: I a tti PP !^ h C I H l W w ispLSI ' 1016/883 in-system programmable Large Scale Integration High-Density Programmable Logic Functional Block D iagram Features • IN-SYSTEM PROGRAM M ABLE HIGH-DENSITY LOGIC — — — — — — M IL-STD-883 Version of th e ispLS11016
|
OCR Scan
|
PDF
|
IL-STD-883
ispLS11016
44-Pin
ispLS11016/883
|