MT4C400 Search Results

5962-9084703MNA

Abstract: JEDEC MO-110 ras 0910 5v RAS 0610
Contextual Info: DRAM MT4C4001J Austin Semiconductor, Inc. PIN ASSIGNMENT 1 MEG x 4 DRAM Top View Fast Page Mode DRAM 20-Pin DIP (C, CN) AVAILABLE AS MILITARY SPECIFICATIONS DQ1 DQ2 WE\ RAS\ A9 A0 A1 A2 A3 Vcc • SMD 5962-90847 • MIL-STD-883 FEATURES • Industry standard x4 pinout, timing, functions, and

EDO DRAM

Contextual Info: 1 MEG x 4 EDO DRAM M IC R O N I TFCHNOl.GOY l';C DRAM MT4C4007J FEATURES PIN ASSIGNMENT Top View Single +5V ±10% pow er supply JEDEC-standard pinout and packages High-performance CMOS silicon-gate process All inputs, outputs and clocks are TTL-compatible

Contextual Info: MT4C4004J 1 MEG X 4 DRAM M IC R O N DRAM 1 MEG x 4 DRAM FEATURES _ • Four independent CAS controls, allowing individual manipulation to each of the four data Input/Output ports DQ1 through DQ4 . • Offers a single chip solution to byte level parity for 36bit words when using 1 Meg x 4 DRAMs for memory

MT4C4007JDJ-6

Abstract: MT4C4007JDJ-6L A4 marking EDO DRAM
Contextual Info: OBSOLETE 1 MEG x 4 EDO DRAM MT4C4007J DRAM FEATURES PIN ASSIGNMENT Top View Single +5V ±10% power supply JEDEC-standard pinout and packages High-performance CMOS silicon-gate process All inputs, outputs and clocks are TTL-compatible Refresh modes: RAS#-ONLY, CAS#-BEFORE- RAS#

Contextual Info: MT4C4004J 1 MEG X 4 DRAM [M IC R O N DRAM 1 MEG x 4 DRAM 2 5V, QUAD CAS PARITY, FAST PAGE MODE _ PIN ASSIGNM ENT Top View • Four independent CAS controls, allow ing individual m anipulation to each of the four data in p u t/o u tp u t ports (DQ1 through DQ4).

4c4007

Abstract: 4007J
Contextual Info: MT4C4007J L 1 MEG X 4 DRAM |u iic n o N 1 MEG x 4 DRAM DRAM 5V, EDO PAGE MODE, OPTIONAL EXTENDED REFRESH FEATURES PIN ASSIGNMENT (Top View) • • • • • S in g le + 5 V ± 1 0 % p o w er su p p ly JE D E C -sta n d a rd p in o u t and p ack ag es H ig h -p erfo rm a n ce C M O S silico n -g ate process

1003 ic

Contextual Info: MICRON TECHNOLOGY INC 3flE D blllSMR 0005E07 1 H M R N ADVANCE T-4£-2l-l7 4 MEG X 4 DRAM DRAM FAST PAGE MODE: MT4C40004 STATIC COLUMN: MT4C40005 FEATURES PIN ASSIGNMENT Top View • Industry standard x4 pinout, timing, functions and packages • High performance, CMOS silicon gate process

marking djw

Contextual Info: |U |IC =R O N MT4C4005 1 MEG x 4 DRAM FAST PAGE MODE, WRITE-PER-BIT FEATURES • Industry standard x4 pinout, timing, functions and packages • High performance, CMOS silicon gate process • Single +5V±10% power supply • Low power, 3mW standby; 225mW active, typical

W9C 08

Abstract: marking W9C MT4C400
Contextual Info: SSE D MICRON TECHNOLOGY INC blllSMT □ 0 G S 7 M C1 3T7 M N R N MT4C4001J 883C 1 MEG X 4 DRAM IC Z R O N MILITARY DRAM 1 MEG X 4 DRAM FAST PAGE MODE PIN ASSIGNMENT Top View • SMD 5962-90847, Class M • JAN 5962-90847, Class B • MIL-STD-883, Class B

fast page mode dram controller

Abstract: MT4C4001J
Contextual Info: MT4C4001J 883C 1 MEG x 4 DRAM AUSTIN SEMICONDUCTOR, INC. DRAM 1 MEG x 4 DRAM FAST PAGE MODE AVAILABLE AS MILITARY SPECIFICATIONS PIN ASSIGNMENT Top View • SMD 5962-90847 • MIL-STD-883 FEATURES • Industry standard x4 pinout, timing, functions and packages

Contextual Info: MICR ON S E M I C O N D U C T O R INC b3E D • b l l l S M T D D D V bb ? 51b ■ MRN MT4C4004J 1 MEG x 4 DRAM I^HCRON DRAM 1 MEG x 4 DRAM QUAD CAS PARITY, FAST-PAGE-MODE FEATURES _ PIN ASSIGNMENT Top View • Four independent CAS controls, allowing individual

Contextual Info: MT4C4001 J L 1 MEG X 4 DRAM (M IC R O N DRAM 1 MEG x 4 DRAM DRAM STANDARD OR LOW POWER, EXTENDED REFRESH FEATURES • 1,024-cycle refresh distributed across 16ms (MT4C4001J) or 128ms (MT4C4001J L) • Industry-standard x4 pinout, timing, functions and packages

Contextual Info: MT4C4004J 1 MEG X 4 DRAM |U|IC=RON DRAM 1 MEG x 4 DRAM FEATURES _ • Four independent CAS controls, allowing individual manipulation to each of the four data input/output ports DQ1 through DQ4 . • Offers a single chip solution to byte level parity for 36bit words when using 1 Meg x 4 DRAMs for memory

Contextual Info: MT4C4001 J S 1 MEG X 4 DRAM (MICRON DRAM 1 MEG x 4 DRAM 5V, STANDARD OR SELF REFRESH • 1,024-cycle refresh distributed across 16ms (MT4C4001J) or 128ms (MT4C4001J S) • Industry-standard pinout, timing, functions and packages • High-perform ance CM OS silicon-gate process

T4C4001JDJ-6

Abstract: mt4c4001
Contextual Info: MT4C4001 J S 1 MEG X 4 DRAM [M IC R O N DRAM 1 MEG X 4 DRAM FEATURES • 1,024-cycle refresh distributed across 16ms (MT4C4001J) or 128ms (M T4C4001J S) • Industry-standard pinout, timing, functions and packages • High-perform ance CM O S silicon-gate process

marking wml

Abstract: j-l003 marking WMM C1994 MT4C4001 MT4C4001J MT4C4001JDJ-6
Contextual Info: M ir n O M I .“ hT M T 4C 4001J S 1 M EG X 4 D R A M 1 MEG DRAM X 4 DRAM STANDARD OR SELF REFRESH a J3 > FEATURES • 1,024-cycle refresh distributed across 16ms (MT4C4001J) or 128ms (MT4C4001J S) • Industry-standard pinout, timing, functions and packages

Contextual Info: 1 MEG X 4 FPM DRAM MICRON I TECHNOLOGY. INC. DRAM M T4C 4001J FEATURES • 1,024-cycle refresh distributed across 16ms MT4C4001J or 128ms (MT4C4001J L) • Industry-standard pinout, timing, functions and packages • High-performance CMOS silicon-gate process

CC3-100

Contextual Info: [M ICRON MT4C4003J 1 MEG X 4 DRAM DRAM 1 MEG X 4 DRAM DRAM S T A T IC -C O L U M N FEATURES • Industry-standard x4 pinout, timing, functions and packages • High-performance CMOS silicon-gate process • Single +5V ±10% power supply • Low power, 3mW standby; 275mW active, typical

LIS-1024

Contextual Info: OBSOLETE M I C R O N 1 ^cnllvZ DRAM E G x 4 MT4C4007J FEATURES PIN ASSIGNMENT Top View • • • • • Single +5V +10% pow er supply JED EC-standard pinout and packages H igh-perform ance CM OS silicon-gate process All inputs, outputs and clocks are TTL-com patible

MT4C4007JDJ-6

Abstract: MT4C4007J MT4C4007JDJ-6L
Contextual Info: MT4C4007J L 1 MEG x 4 DRAM TECHNOLOGY, INC. 1 MEG x 4 DRAM DRAM 5V, EDO PAGE MODE, OPTIONAL EXTENDED REFRESH FEATURES Single +5V ±10% power supply JEDEC-standard pinout and packages High-performance CMOS silicon-gate process All inputs, outputs and clocks are TTL-compatible

MT4C40004

Abstract: 4096-cycle
Contextual Info: ADVANCE X 4 DRAM FAST PAGE MODE: MT4C40004 MT4C40005 STATIC COLUMN: FEATURES PIN ASSIGNMENT Top View • Industry standard x4 pinout, tim ing, functions and packages • H igh perform ance, C M O S silicon gate process • Single pow er supply : +5V ±10% or +3.3V ±10%

B1115

Abstract: mt4c4001 MT4C4001JDJ-6 4c4001 MT4C4001J JCSR
Contextual Info: MICRON SEMICONDUCTOR INC b3E D • b l l l S 4 cì 0D07b2tì 4D2 BURN MT4C4001 J L 1 MEG X 4 DRAM M IC R O N DRAM 1 MEG x 4 DRAM DRAM STANDARD OR LOW POWER, EXTENDED REFRESH FEATURES • 1,024-cycle refresh distributed across 16ms (MT4C4001J) or 128ms (MT4C4001J L)

Contextual Info: AU ST IN S E M I C O N D U C T O R INC bDE D • T D D 2 1 1 7 D 0 G D 1 7 C1 7bG ■ AUST MT4C4001J 883C 1 MEG X 4 DRAM I^ICRON is MILITARY DRAM 1 MEG X 4 DRAM FAST PAGE MODE DRAI AVAILABLE AS MILITARY SPECIFICATIONS • SMD 5962-90847, Class M • JAN 5962-90847, Class B

Contextual Info: [m i c r o MT4C4003J 1 MEG X 4 DRAM n DRAM 1 MEG X 4 DRAM STATIC COLUMN FEATURES • Industry standard x4 pinout, timing, functions and packages • High-performance, C M O S silicon-gate process • Single +5V ±10% p ow er supply • L o w power, 3 m W standby; 225mW active, typical