MT4C1024D Search Results

Contextual Info: MT6D118 1 MEG X 18 DRAM MODULE M IC R O N 1 MEG X 18 DRAM FAST PAGE MODE FEATURES • Industry standard pinout in a 72-pin single-in-line package • High-performance, CMOS silicon-gate process • Single 5V ±10% power supply • All device pins are fully TTL compatible

Contextual Info: |U|IC=ROÍNJ 1 MEG DRAM MODULE X 8 MT8D18 DRAM MODULE 1 MEG X 8 DRAM FAST PAGE MODE MT8D18 LOW POWER, EXTENDED REFRESH (MT8D18L) FEATURES • Industry standard pinout in a 30-pin single-in-line package • High-perform ance, CM OS silicon-gate process • Single 5V ±10% power supply

Contextual Info: |U |IC R O N lEG X 1 MEG DRAM MODULE MT6D118 18 DRAM MODULE X 18 DRAM FAST-PAGE-MODE FEATURES PIN ASSIGNMENT Top View • Industry-standard pinout in a 72-pin single-in-line package • High-performance CM OS silicon-gate process • Single 5V ±10% power supply

T3D19

Abstract: 30-pin simm memory "16m x 8" MT4C1024DJ MT3019 MT4C4001 30-pin SIMM
Contextual Info: [M IC R O N 1 MEG X MT3D19 9 DRAM MODULE 1 MEG x 9 DRAM DRAM MODULE FAST PAGE MODE MT3D19 LOW POWER, EXTENDED REFRESH (MT3D19 L) FEATURES PIN ASSIGNMENT (Top View) • Industry standard pinout in a 30-pin single-in-line memory module • High-performance, CM OS silicon-gate process

Cherie

Abstract: t3d25
Contextual Info: |U 1IC =R O N DRAM k - _ Ä 2 56K X MT3D2569 9 DRAM MODULE 256K x 9 DRAM _ FAST PAGE MODE MT3D2569 LOW POWER, F EXTENDED V T F N n P D RF REFRESH (MT3D2569 L) M O D IW 1I^ FL — FEATURES MARKING • Timing 60ns access 70ns access 80ns access -6 -7 -8 • Packages

t3d19

Abstract: MT4C1024DJ a7020
Contextual Info: [MICRON □PAM _ _ _ _ . . _ 1 MEG X MT3D19 9 DRAM MODULE 1 MEG x 9 DRAM _ FAST-PAGE-MODE MT3D19 LOW POWER, EXTENDED REFRESH (M T3D19 L) MODULE \J L. t . IVIv y U FEATURES PIN ASSIGNMENT (Top View) • Industry-standard pinout in a 30-pin single-in-line

MT3D19

Abstract: MT4C4001 30-pin SIMM nsi 60 jg
Contextual Info: Ü H Ü MI CR ON T E C H N O L O G Y INC 3ûE D blUSM T 0QGS3SS S BIMRN f'.'ÜWI1Vt?»MBJHMU- '•MIWÆ' V •*' '» ¡PB ilr'itfliilri 1 MEG DRAM MODULE 9 DRAM FAST PAGE MODE FEATURES PIN ASSIGNMENT Top View • Industry standard pinout in a 30-pin single-in-line

Contextual Info: MICR ON S E M I C O N D U C T O R INC b3E D • b l l l S M T D D D V bb ? 51b ■ MRN MT4C4004J 1 MEG x 4 DRAM I^HCRON DRAM 1 MEG x 4 DRAM QUAD CAS PARITY, FAST-PAGE-MODE FEATURES _ PIN ASSIGNMENT Top View • Four independent CAS controls, allowing individual

Contextual Info: M ICRON SEM ICONDUCTOR INC b3E D M IC R O N WÊ b lllS M T 1 MEG X 0 G D 7 cì b G b O 1» « P I R N MT3D19 9 DRAM MODULE 1 MEG X 9 DRAM DRAM MODULE FAST-PAGE-MODE MT3D19 LOW POWER, EXTENDED REFRESH (MT3D19 L) FEATURES • Industry-standard pinout in a 30-pin single-in-line

MT4C1024

Abstract: micron MT4C
Contextual Info: MICRON SEMICONDUCTOR INC b3E S • hlllSMR G007544 Ô3Ô B U R N MT4C1024 L 1 MEG X 1 DRAM |U|C=RON DRAM 1 MEG x 1 DRAM FEATURES PIN ASSIGNMENT (Top View) OPTIONS MARKING • Timing 60ns access 70ns access 80ns access -6 -7 -8 • Packages Plastic DIP (300 mil)

Contextual Info: MT4C4004J 1 MEG X 4 DRAM |U|IC=RON DRAM 1 MEG x 4 DRAM FEATURES _ • Four independent CAS controls, allowing individual manipulation to each of the four data input/output ports DQ1 through DQ4 . • Offers a single chip solution to byte level parity for 36bit words when using 1 Meg x 4 DRAMs for memory

T3D19

Contextual Info: |V|IC =R O N 1 MEG DRAM MODULE 1 MEG X X M T3D19 9 DRAM M O D ULE 9 DRAM FAST-PAGE-MODE MT3D19 LOW POWER, EXTENDED REFRESH (MT3D19 L) FEATURES • Industry-standard pinout in a 30-pin single-in-line memory module • High-performance CMOS silicon-gate process

MT4C1024

Contextual Info: MT4C1024 L 1 MEG X 1 DRAM |U|IC=RON 1 MEG x 1 DRAM DRAM STANDARD OR LOW POWER, EXTENDED REFRESH • 512-cycle refresh in 8ms (MT4C1024) or 64ms (MT4C1024 L) • Industry-standard xl pinout, timing, functions and packages • High-performance CMOS silicon-gate process

T4C400

Abstract: mt4c4004jdj
Contextual Info: M T4C4004J 1 MEG X 4 DRAM l^ldRON DRAM 1 MEG x 4 DRAM QUAD CAS PARITY, FAST PAGE MODE FEATURES _ • Four independent C A S controls, allo w ing in d ivid u al m anipulation to each of the four data In p u t/O u tp ut ports DQ1 through DQ4 . • Offers a single chip solution to byte level parity for 36bit words w hen using 1 M eg x 4 D R A M s for m emory

MT4C1024DJ

Abstract: E1994
Contextual Info: |v iic : r M T12D136 1 MEG X 36, 2 MEG x 18 DRAM M O D ULE o n □RAM _ MODULE • ■ IV / W W ^ 1 MEG x 36>2 MEG x 18 FAST PAGE MODE MT12D136 lo w p o w e r, F EXTENDED Y T F M D F n R REFRESH F (MT12D136 L) I— FEATURES PIN ASSIGNMENT (Top View) OPTIONS

mt4c1024d

Contextual Info: M ICRO N 2 MEG MT24D236 36, 4 MEG x 18 DRAM MODULE X DRAM 2 MEG x 36, 4 MEG x 18 _ _^ FAST PAGE MODE MT24D236 LOW POWER, EXTENDED REFRESH (MT24D236 L) MODULE m _ V U . _ _ U b L i FEATURES • Industry-standard pinout in a 72-pin single-in-line package

Contextual Info: M IC R O N 1 MEG X 8 MT8D18 DRAM MODULE 1 MEG X 8 DRAM DRAM MODULE FAST-PAGE-MODE (MT8D18 LOW POWER, EXTENDED REFRESH (MT8D18L) FEATURES PIN ASSIGNMENT (Top View) • In d u stry -stan d ard p in o u t in a 3 0 -p in sin g le-in -lin e p ack ag e • H ig h -p erfo rm a n ce C M O S silico n -g a te p ro cess

MT4C1024DJ-7

Contextual Info: MT4C1024 L 1 MEG X 1 DRAM MICRON • SEMICONDUCTOR. iHC 1 MEG x 1 DRAM DRAM STANDARD OR LOW POWER, EXTENDED REFRESH FEATURES • 512-cycle refresh in 8ms (MT4C1024) or 64ms (MT4C1024 L) • Industry-standard x l pinout, timing, functions and packages • High-performance CMOS silicon-gate process

MT9D19

Contextual Info: [m ic r o n □PAM 1 MEG X MT9D19 9 DRAM MODULE 1MEG x 9 d ram _ FAST-PAGE-MODE MT9D19 LOW POWER, EXTENDED REFRESH (MT9D19 L) M O D U LLE . I— IVI V / FEATURES • Industry-standard pinout in a 30-pin single-in-line package • High-performance CMOS silicon-gate process

T4C4004JDJ

Abstract: marking W7F
Contextual Info: MT4C4004J 1 MEG X 4 DRAM I^ IIC R O N DRAM 1 MEG x 4 DRAM FEATURES _ PIN ASSIGNMENT Top View • Four independent CAS controls, allowing individual manipulation to each of the four data inpu t/output ports (DQ1 through DQ4). • Offers a single chip solution to byte level parity for 36bit words when using 1 M eg x 4 DRAMs for memory

Contextual Info: |V M = R O N 2 MEG □RAM _ _ _ _ _ _ _ _ MODULE •■ ■ V W w U MT24D236 36, 4 MEG x 18 DRAM M ODULE X 2 MEG x 36’ 4 MEG x 18 FAST-PAGE-MODE MT24D236 LOW POWER, P EXTENDED Y T P M n r n RREFRESH F (MT24D236 L) ^ FEATURES • Industry-standard p in o u t in a 72-pin single-in-line

Contextual Info: M IC R O N I m - n u iN M T12D136 1 MEG X 36, 2 MEG X 18 DRAM M ODULE 1 MEG X 36, 2 MEG X 18 DRAM MODULE NEW I FAST PAGE MODE MT12D136 LOW POWER, EXTENDED REFRESH (MT12D136 L) FEATURES PIN ASSIGNMENT (Top View) OPTIONS 72-Pin SIMM (T-19) MT12D136M/G o MARKING

MT42C4256Z

Contextual Info: l i f- V nib MICRON • 512K X MT20D51240 40 DRAM M O DULE 512K X 40 DRAM FAST PAGE MODE MT20D51240 LOW POWER, EXTENDED REFRESH (MT20D51240 L) FEATURES • • • • • • • • • 72-pin single-in-line package High-performance, CMOS silicon-gate process.

Contextual Info: M IC R O N 1 MEG □RAM _ MODULE m V /U U L iU MT12D136 36, 2 MEG x 18 DRAM MODULE X 1 MEG x 36, 2 MEG x 18 FAST-PAGE-MODE MT12D136 lo w p o w e r, EXTENDED REFRESH (MT12D136 L) FEATURES PIN ASSIG N M EN T (Top View) • Industry-standard pinout in a 72-pin single-in-line