R36W
Abstract: lnk303 samsung ltn LD3130 CRC10 MXT3010 R44-R47 M 8012 R54-R55 t9354
Text: MXT3010 Reference Manual Version 4.1 Order Number: 100108-05 October 1999 Copyright c 1999 by Maker Communications, Inc. All rights reserved. Printed in the United States of America. The information in this document is believed to be correct, however, the
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MXT3010
16-bit
MXT3010
R36W
lnk303
samsung ltn
LD3130
CRC10
R44-R47
M 8012
R54-R55
t9354
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APM 4317
Abstract: Installation guide for RBS g24 Data Module max 202 rs232 driver old fm radio diagram EASY256 MUNICH256 Mainboard Schematics history MUNICH256F rs232 abel sender receiver
Text: Tool Descri ption , DS 1, Septem ber 2000 E A S Y 2 56 E v a lu a tio n S y s te m f or M UN IC H2 5 6 /F / F M Ve rsi o n 2. 1 Da ta c o m N e v e r s t o p t h i n k i n g . Edition 09.00 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany
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D-81541
EASY256
APM 4317
Installation guide for RBS
g24 Data Module
max 202 rs232 driver
old fm radio diagram
EASY256
MUNICH256
Mainboard Schematics history
MUNICH256F
rs232 abel sender receiver
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8051 opcode
Abstract: AN2131QC cypress ez-usb AN2131QC interrupt 8051 AN2135 8051 examples AN2131, datasheet AN2131Q AN2135SC 8051
Text: EZ-USB Technical Reference Manual Cypress Semiconductor 3901 North First Street San Jose, CA 95134 Tel.: 800 858-1810 (toll-free in the U.S.) (408) 943-2600 www.cypress.com Cypress Disclaimer Agreement The information in this document is subject to change without notice and should not be construed as a commitment by Cypress Semiconductor Corporation Incorporated. While
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MRC D6 16A
Abstract: No abstract text available
Text: Cover Marvell PXA270 Processor Developers Manual Doc. No. MV-S301039-00 , Rev. A April 2009 Marvell. Moving Forward Faster Released PXA270 Processor Developers Manual Document Conventions Note: Provides related information or information of special importance.
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PXA270
MV-S301039-00
PXA270
MV-S301039-00
MRC D6 16A
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oq 0051
Abstract: 28D7 16C622 AN729 0CB1
Text: LinBsApNt.book Page 1 Wednesday, October 11, 2000 11:32 AM AN729 LIN Protocol Implementation Using PICmicro MCUs Authors: ever, instead of having a clock line, each byte is marked via start and stop bits and the individual bits are asynchronously timed like RS232.
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AN729
RS232.
DS00729A-page
oq 0051
28D7
16C622
AN729
0CB1
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CY7C64603-80NC
Abstract: cy7c64613-52nc anchor CY7C64601-52NC CY7C64603-128NC CY7C64603-52NC CY7C64613-128NC CY7C64613-52NC CY7C64613-80NC ANCHOR CHIPS LA 7840 DIAGRAM
Text: EZ-USB FX Technical Reference Manual • Cypress Semiconductor • Interface Products Division • • 15050 Avenue of Science • Suite 200 • San Diego, CA 92128 • Cypress Disclaimer Agreement The information in this document is subject to change without notice and should not be construed as a commitment by Cypress Semiconductor Corporation Incorporated. While
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Untitled
Abstract: No abstract text available
Text: 8201, 8202, 8203, 8204 Acceleration Processor Data Sheet Exar Confidential DS-0157-05 April 16, 2012, Exar , Inc. All rights reserved. 04/12 No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form by any means without the written permission of Exar Corporation.
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DS-0157-05
8201I
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bip 109
Abstract: 78P7200 CN8223 CN8223EPF
Text: CN8223 ATM Transmitter/Receiver with UTOPIA Interface The CN8223 ATM Transmitter/Receiver with UTOPIA Level 1 interface provides a single-access ATM service termination for User-to-Network UNI and Network-to-Network Interfacing (NNI) in conformance with ATM Forum UNI and NNI
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CN8223
CN8223
TR-TSV-000772,
TR-TSV-000773,
TR-NWT-000253,
T1S1/92-185;
bip 109
78P7200
CN8223EPF
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BT8222KPF
Abstract: atm header error checking 78P7200 CN8223 CN8223EPF e3 frame formatter
Text: CN8223 ATM Transmitter/Receiver with UTOPIA Interface The CN8223 ATM Transmitter/Receiver with UTOPIA Level 1 interface provides a single-access ATM service termination for User-to-Network UNI and Network-to-Network Interfacing (NNI) in conformance with ATM Forum UNI and NNI
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CN8223
CN8223
TR-TSV-000772,
TR-TSV-000773,
TR-NWT-000253,
T1S1/92-185;
BT8222KPF
atm header error checking
78P7200
CN8223EPF
e3 frame formatter
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VHDL code for ADC and DAC SPI with FPGA
Abstract: VHDL code for ADC and DAC SPI with FPGA spartan 3 XAPP876 vhdl code for parallel to serial converter 12-bit ADC interface vhdl code for FPGA picoblaze UG347 DS202 JESD204 JESD204A
Text: Application Note: Virtex-5 Family Virtex-5 FPGA Interface to a JESD204A Compliant ADC XAPP876 v1.0 September 18, 2009 Author: Marc Defossez Summary This application note describes how to interface the Virtex -5 LXT, SXT, TXT, and FXT devices featuring GTP/GTX transceivers to an analog-to-digital (ADC) converter compliant to JEDEC
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JESD204A
XAPP876
JESD204A)
JESD204
JESD204A
VHDL code for ADC and DAC SPI with FPGA
VHDL code for ADC and DAC SPI with FPGA spartan 3
XAPP876
vhdl code for parallel to serial converter
12-bit ADC interface vhdl code for FPGA
picoblaze
UG347
DS202
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sony ps3 eye camera
Abstract: PXA272 ED101 transistor PXA271 PXA27x ss100 transistor NPCE 795 AF117 transistor PXA210 relays STPI 310
Text: Intel PXA27x Processor Family Developer’s Manual January 2006 Order Number: 280000-003 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTELR PRODUCTS. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS
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PXA27x
Index-36
sony ps3 eye camera
PXA272
ED101 transistor
PXA271
ss100 transistor
NPCE 795
AF117 transistor
PXA210
relays STPI 310
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VOLVO driver information module
Abstract: 3CA6 00829 18AF 1B31 294a A 393F Volvo 16C622 AN729
Text: AN729 LIN Protocol Implementation Using PICmicro MCUs Authors: ever, instead of having a clock line, each byte is marked via start and stop bits and the individual bits are asynchronously timed like RS232. Dan Butler Thomas Schmidt Thorsten Waclawczyk Microchip Technology Inc.
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AN729
RS232.
D-81739
VOLVO driver information module
3CA6
00829
18AF
1B31
294a
A 393F
Volvo
16C622
AN729
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"AN2131S"
Abstract: AN2136 2131S AN2135S AN2135SC AN2122S tcon transmitter AN2122 R8051 AN2131S
Text: EZ-USB Series 2100 Technical Reference Manual Table of Contents 1 Introducing EZ-USB . 1-1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 1.13 1.14 1.15 1.16 1.17 1.18 1.19 Introduction . 1-1
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cypress ez-usb AN2131QC
Abstract: AN2135SC AN2131QC AN2135S AN2131 AN2131, datasheet AN2131Q EZ-USB AN2131Q 1B80 8051 opcode with mnemonic sheet
Text: The EZ-USBTM Integrated Circuit Technical Reference The information in this document is subject to change without notice and should not be construed as a commitment by Cypress Semiconductor Corporation. While reasonable precautions have been taken, Cypress
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VHDL code for ADC and DAC SPI with FPGA spartan 3
Abstract: VHDL code for ADC and DAC SPI with FPGA 12-bit ADC interface vhdl code for FPGA direct sequence spread spectrum virtex JESD204 XAPP876 Xilinx ml507 prbs jesd VHDL code for high speed ADCs using SPI with FPGA virtex 4 date code for ADC
Text: Application Note: Virtex-5 Family Virtex-5 FPGA Interface to a JESD204A Compliant ADC XAPP876 v1.0.1 February 22, 2010 Author: Marc Defossez Summary This application note describes how to interface the Virtex -5 LXT, SXT, TXT, and FXT devices featuring GTP/GTX transceivers to an analog-to-digital (ADC) converter compliant to JEDEC
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JESD204A
XAPP876
JESD204A)
JESD204
JESD204A
VHDL code for ADC and DAC SPI with FPGA spartan 3
VHDL code for ADC and DAC SPI with FPGA
12-bit ADC interface vhdl code for FPGA
direct sequence spread spectrum virtex
XAPP876
Xilinx ml507 prbs
jesd
VHDL code for high speed ADCs using SPI with FPGA
virtex 4 date code for ADC
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N8222
Abstract: 28-22-21 bt8222
Text: Bt8222 ATM Transmitter/Receiver with UTOPIA Interface The Bt8222 ATM Transmitter/Receiver with UTOPIA Level 1 interface provides a single-access ATM service termination for User-to-Network UNI and Network-to-Network Interfacing (NNI) in conformance with ATM Forum UNI and NNI
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Bt8222
Bt8222
TR-TSV-000772,
TR-TSV-000773,
TR-NWT-000253,
T1S1/92-185;
N8222
28-22-21
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AN2135S
Abstract: cypress ez-usb AN2131QC intel 8052 AN2121S 1C80-1CBF C51 Family by keil AN2122S SM210 AN2131SC NEC PX4
Text: EZ-USB Series 2100 Technical Reference Manual Table of Contents 1 Introducing EZ-USB . 1-1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 1.13 1.14 1.15 1.16 1.17 1.18 1.19 Introduction . 1-1
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AN2126TC
AN2131SC
AN2135SC
AN2136SC
AN2131QC
AN2135S
cypress ez-usb AN2131QC
intel 8052
AN2121S
1C80-1CBF
C51 Family by keil
AN2122S
SM210
NEC PX4
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3CA6
Abstract: VOLVO driver information module DS00729 Volvo Waclawczyk MOD256 24 pin K-line 00829 294a data engine BMW
Text: AN729 LIN Protocol Implementation Using PICmicro MCUs Authors: ever, instead of having a clock line, each byte is marked via start and stop bits and the individual bits are asynchronously timed like RS232. Dan Butler Thomas Schmidt Thorsten Waclawczyk Microchip Technology Inc.
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AN729
RS232.
DS00729A-page
3CA6
VOLVO driver information module
DS00729
Volvo
Waclawczyk
MOD256
24 pin K-line
00829
294a
data engine BMW
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L8222
Abstract: OQ 051
Text: 1.0 Product Description 1.1 Introduction Figure 1-1 is a detailed block diagram of the Bt8222. For transmission from the host system, octet-wide data is input from the UTOPIA or FIFO ports. The host data is assembled into ATM cells and then formatted for serial line transmission
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Bt8222.
L822201
L8222
OQ 051
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siemens b 58 468 la intel 80
Abstract: siemens "b 58 468" la intel 80 siemens MFAB alco ff 4-4 dah PEB2055n CDS2C MOD1024 siemens b 58 468 la intel 80 0/siemens "b 58 468" la intel 80
Text: SIEMENS Extended PCM Interface Controller EPIC PEB 2055 CMOS 1C Preliminary Data 1 Introduction 1.1 Features * Board Controller for up to 32 ISDN or 64 voice subscribers * Nonblocking switch tor 128 channels (16.32. or 64 kbps bandwidth) * Two consecutive 64 kbps channels can be switched as a single 128 kbps channel.
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023SbQS
E35b05
Q67100
Q67100H
235b05
0G703
siemens b 58 468 la intel 80
siemens "b 58 468" la intel 80
siemens
MFAB
alco ff 4-4 dah
PEB2055n
CDS2C
MOD1024
siemens b 58 468 la intel 80
0/siemens "b 58 468" la intel 80
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Untitled
Abstract: No abstract text available
Text: SIEMENS PEB 20550 PEF 20550 Overview 1 Overview The PEB 20550 Extended Line Card Controller is a highly integrated controller circuit optimized for line card and key system applications. It combines all functional blocks necessary to manage up to 32 digital (ISDN or proprietary) or 64 analog subscribers.
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fi235bG5
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dm024
Abstract: A992 transistor and its equivalent LB 11917
Text: LOGIC LEA300K Embedded Array 5 Volt ASIC Products Databook O c to b e r 1994 This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation.
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LEA300K
DB04-000048-00,
D-102
FALU32
32-bit
FMPY32
FALU32P
dm024
A992 transistor and its equivalent
LB 11917
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DM024
Abstract: oti 2168 CM17B transistor bf 175
Text: 5304804 LSI LOGIC □□mb7A LCA300K G ate Array 5 V olt Series P roducts D atabook Oct ober 1993 f 55b 5304604 0014b7T 4^2 * L L C Preface The LCA300K Gate Array Product Series Databook is written for logic and system designers who wish to use LSI Logic’s 0.6-micron gate
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LCA300K
0014b7T
120x32
FALU32
32-bit
FMPY32
FALU32P
DM024
oti 2168
CM17B
transistor bf 175
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headland 386
Abstract: transistor zo 607 MA 7S b2211 full subtractor using ic 74138
Text: LOGIC LCB300K Cell-Based 5 Volt ASIC Products Databook October 1994 This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation.
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LCB300K
DB04-000049-00,
D-102
I40lg
headland 386
transistor zo 607 MA 7S
b2211
full subtractor using ic 74138
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