pSOS
Abstract: 460016 8572a 79S381 79S465 R3000 R3051 R3052 R3081 R36100
Text: Real-Time Operating Systems Integrated Systems, Inc. pSOSystem/MIPS Accelerated Technology, Inc. Software Development Tools Embedded Development for MIPS Processors Standard Features Description pSOSystem/MIPS provides a complete embedded application cross-development environment for the MIPS
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R3000
R4000
4600-DRx--64
8-to-32
4600-FCx--64
4600-VCAP--NTSC/PAL
4600-VDIP--NTSC/PAL
Dimensions--13
600-12A/D--12
it-30
pSOS
460016
8572a
79S381
79S465
R3051
R3052
R3081
R36100
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MIPS R3000A
Abstract: SN00177 SN00174 16X16 BIT RISC PROCESSOR MIPS r3000 Nihon Dempa Kogyo Co., Ltd. CS4216 LQFP208 philips monochrome monitor PR31500ABC
Text: INTEGRATED CIRCUITS MIPS PR31500 Poseidon embedded processor Preliminary specification Version 0.1 Philips Semiconductors 1996 Sep 24 Philips Semiconductors Preliminary specification MIPS PR31500 Poseidon embedded processor Version 0.1 GENERAL DESCRIPTION
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PR31500
32-bit
R3000
R3000A
PR31500
MIPS R3000A
SN00177
SN00174
16X16 BIT RISC PROCESSOR
MIPS r3000
Nihon Dempa Kogyo Co., Ltd.
CS4216
LQFP208
philips monochrome monitor
PR31500ABC
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mips r3000 pin diagram
Abstract: "ir receiver" preamp PCMCIA SRAM Card R3000 processor CS4216 LQFP208 PR31100 PR31100ABC R3000 UCB1100
Text: INTEGRATED CIRCUITS MIPS PR31100 Highly integrated embedded processor Preliminary specification Version 1.2 Philips Semiconductors 1996 Aug 07 Philips Semiconductors Preliminary specification MIPS PR31100 Highly integrated embedded processor Version 1.2 GENERAL DESCRIPTION
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PR31100
32-bit
R3000
PR31100
mips r3000 pin diagram
"ir receiver" preamp
PCMCIA SRAM Card
R3000 processor
CS4216
LQFP208
PR31100ABC
UCB1100
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diagram tv Philips plasma 42 logic board
Abstract: MIPS r3000 IBS UART PCMCIA SRAM Card CS4216 LQFP208 PR31100 PR31100ABC R3000 UCB1100
Text: Philips Semiconductors Preliminary specification MIPS PR31100 Highly integrated embedded processor Version 1.2 GENERAL DESCRIPTION FEATURES PR31100 Processor is a single-chip, low-cost, integrated embedded processor consisting of MIPS R3000 core and system support logic
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PR31100
R3000
PR31100
711GflEb
LQFP208:
diagram tv Philips plasma 42 logic board
MIPS r3000
IBS UART
PCMCIA SRAM Card
CS4216
LQFP208
PR31100ABC
UCB1100
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SAD 512d
Abstract: MIPS embedded GT-64111 NEC VR4300
Text: Galileo. GT-64111 Universal PCI System Controller for MIPS Processors Please contact Galileo Technology for possible updates before finalizing a design FEATURES • Integrated PCI system controller for high-performance embedded applications • Supports all embedded 32-bit bus 64-bit MIPS CPUs
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32-bit
64-bit
RV4640
RV4650
RM5230
Vr4300
66MHz
512MB
SAD 512d
MIPS embedded
GT-64111
NEC VR4300
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adm5120p
Abstract: usb ethernet RS232 single chip switch ADM5120 USB voip PIN DIAGRAM OF RJ45 to usb usb ethernet single chip switch MIPS 4KC
Text: Product Brief ADM5120P System on Chip SoC Network Processor The ADM5120P is a high performance, integrated and highly flexible SOC (System-On-Chip) network processor. Internally, the ADM5120P consists of a high performance (227 MIPS) embedded MIPS CPU, an embedded switch engine, a five
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ADM5120P
ADM5120P
10/100M
B000-H0000-X-X-7600
usb ethernet RS232 single chip switch
ADM5120
USB voip
PIN DIAGRAM OF RJ45 to usb
usb ethernet single chip switch
MIPS 4KC
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R2000 mips
Abstract: R2000 R3000 Modular Embedded Computer Library 1989
Text: Ada Development Tools DDC-I DACS MIPS Ada Cross Compiler System The DDC-I-Ada Compiler System for R2000 and R3000 MIPS™ processors, DACS™-MIPS, is designed for development of real-time embedded applications. DACS-MIPS is a complete solution containing not only
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R2000
R3000
MIL-STD-1815
DK-2800,
R2000 mips
R3000
Modular Embedded Computer
Library 1989
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ta80960kb
Abstract: LADI 12V VAX-11
Text: 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING POINT UNIT • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped
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80960KB
32-BIT
512-Byte
80960KA
ta80960kb
LADI 12V
VAX-11
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Untitled
Abstract: No abstract text available
Text: PRELIMINARY 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Commercial • High-Performance Embedded Architecture ■ — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■
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80960MC
32-BIT
80-Bit
512-Byte
LAD31
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verilog code for 16 bit risc processor
Abstract: MIPS16 mips vhdl code 4102TM verilog code for 32 bit risc processor vhdl code mips code vhdl code for uart vhdl code for risc processor 32 bit risc processor using vhdl BDMR4102
Text: TinyRISC 4102 MIPS Processor Core Overview The 4102TM TinyRISC MIPS processor core extends LSI Logic’s embedded RISC processor family. This core is the second generation of the widely used TinyRISCTM MIPS processor implementation using the MIPS16, Application
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4102TM
MIPS16,
16-bit
32-bit
MIPS16
MIPS16
85MHz
TR4102
C20027
verilog code for 16 bit risc processor
mips vhdl code
verilog code for 32 bit risc processor
vhdl code mips code
vhdl code for uart
vhdl code for risc processor
32 bit risc processor using vhdl
BDMR4102
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Untitled
Abstract: No abstract text available
Text: 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING POINT UNIT High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz Built-In Interrupt Controller — 31 Priority Levels, 256 Vectors
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80960KB
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512-Byte
132-Lead
80960KB
4fl2bl75
01bb514
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LA07
Abstract: No abstract text available
Text: 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING POINT UNIT • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped
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80960KB
32-BIT
512-Byte
32-Blt
80960KA
LA07
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TA80960KB
Abstract: ADS-132 80960KA 80960KB 80960MC LAD26
Text: 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped
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80960KB
32-BIT
512-Byte
80960KA
80960KB
TA80960KB
ADS-132
80960KA
80960MC
LAD26
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R2000 mips
Abstract: MIL-STD-1815A R2000 R3000 instruction pipeline irix
Text: Ada Development Tools DDC-I DACS MIPS Ada Cross Compiler System Standard Features The DDC-I-Ada Compiler System for R2000 and R3000 MIPS™ processors, DACS™-MIPS, is designed for development of real-time embedded applications. DACS-MIPS is a complete solution containing not only
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R2000
R3000
MIL-STD-1815A)
DK-2800,
R2000 mips
MIL-STD-1815A
R3000
instruction pipeline
irix
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a4490
Abstract: 80960MC A80960MC25 i960 mc errata 80960KA 80960KB M8259A intel packaging handbook 240800
Text: 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Commercial • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ On-Chip Floating Point Unit
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80960MC
32-BIT
80-Bit
512-Byte
LAD31_
A4492-01
A80960MC.
a4490
80960MC
A80960MC25
i960 mc errata
80960KA
80960KB
M8259A
intel packaging handbook 240800
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VAX-11
Abstract: MIPS embedded RRU 32
Text: intj 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped
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80960KB
32-BIT
132-Lead
80-Bit
512-Byte
VAX-11
MIPS embedded
RRU 32
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Untitled
Abstract: No abstract text available
Text: 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING POINT UNIT • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ Built-In Interrupt Controller — 31 Priority Levels, 256 Vectors
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80960KB
32-BIT
512-Byte
132-Lead
80960KB
4fl2bl75
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a4490
Abstract: 80960MC LAD12 80960KA 80960KB M8259A i960 mc errata
Text: PRELIMINARY 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Commercial • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ On-Chip Floating Point Unit
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80960MC
32-BIT
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512-Byte
LAD31_
A4492-01
A80960MC.
a4490
80960MC
LAD12
80960KA
80960KB
M8259A
i960 mc errata
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TA80960KB
Abstract: 2T818 tl741
Text: intJ 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped
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80960KB
32-BIT
132-Lead
80-Bit
512-Byte
TA80960KB
2T818
tl741
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Power Supply Supervisor iw 1688
Abstract: 754for
Text: intei 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Commercial • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ On-Chip Floating Point Unit
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80960MC
32-BIT
80-Bit
512-Byte
80960MC
A80960MC.
Power Supply Supervisor iw 1688
754for
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Untitled
Abstract: No abstract text available
Text: intei 80960KA EMBEDDED 32-BIT MICROPROCESSOR • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached
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80960KA
32-BIT
512-Byte
80960KB
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SA-1100
Abstract: No abstract text available
Text: StrongARM SA-1100 Microprocessor for Embedded Applications Brief Datasheet Product Features The StrongARM* SA-1100 Microprocessor SA-1100 is a device targeted to provide high-performance computing to embedded applications but at consumer electronics pricing with MIPS-per-dollar and MIPS-per-watt
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SA-1100
SA-1100)
32-bit
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a4490
Abstract: 80960MC Intel i960 architecture 80960KA 80960KB M8259A 273123
Text: 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Commercial • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ On-Chip Floating Point Unit
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80960MC
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512-Byte
LAD31_
A4492-01
a4490
80960MC
Intel i960 architecture
80960KA
80960KB
M8259A
273123
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Untitled
Abstract: No abstract text available
Text: ÄEW M i DNHF@IRßM!rilON in y 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Military High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at
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