MAX107ECS Search Results

Transmission Line Balun Transformer

Contextual Info: 19-2007; Rev 0; 5/01 Dual, 6-Bit, 400Msps ADC with On-Chip, Wideband Input Amplifier Features ♦ Two Matched 6-Bit, 400Msps ADCs ♦ Excellent Dynamic Performance 36.7dB SINAD at fIN ≈ 125MHz and fCLK ≈ 400MHz ♦ Typical INL and DNL: ±0.25LSB ♦ Channel-to-Channel Phase Matching: ±0.2°

TAD100

Abstract: MAX105 MAX107 MAX107ECS MAX2108
Contextual Info: 19-2007; Rev 0; 5/01 Dual, 6-Bit, 400Msps ADC with On-Chip, Wideband Input Amplifier Features ♦ Two Matched 6-Bit, 400Msps ADCs ♦ Excellent Dynamic Performance 36.7dB SINAD at fIN ≈ 125MHz and fCLK ≈ 400MHz ♦ Typical INL and DNL: ±0.25LSB ♦ Channel-to-Channel Phase Matching: ±0.2°

Contextual Info: 19-2007; Rev 0; 5/01 Dual, 6-Bit, 400Msps ADC with On-Chip, Wideband Input Amplifier In addition, the MAX107 provides LVDS digital outputs with an internal 6:12 demultiplexer that reduces the output data rate to one-half the sample clock rate. Data is output in two’s complement format. The MAX107 operates from a +5V analog supply and the LVDS output

HP8662A

Abstract: HP8663A H-9 SMA
Contextual Info: 19-2055; Rev 0; 5/01 MAX105 Evaluation Kit Features ♦ Two Matched 6-Bit, 800 Msps ADCs ♦ 0.8Vp-p Input Signal Range ♦ Demultiplexed Differential LVDS Outputs ♦ Square-Pin Headers for Easy Connection of Logic Analyzer to Digital Outputs ♦ Four-layer PC Board with Separate Analog and

Contextual Info: 19-2007; Rev 0; 5/01 Dual, 6-Bit, 400Msps ADC with On-Chip, Wideband Input Amplifier Features ♦ Two Matched 6-Bit, 400Msps ADCs ♦ Excellent Dynamic Performance 36.7dB SINAD at fIN ≈ 125MHz and fCLK ≈ 400MHz ♦ Typical INL and DNL: ±0.25LSB ♦ Channel-to-Channel Phase Matching: ±0.2°

HP16500C

Abstract: GRM36COG101J050AD H-9-SMA mthole1 GETEK equivalent TAJD106K025R BLM21A601R GRM36X7R103K016AD MAX105 47r20
Contextual Info: 19-2055; Rev 0; 5/01 MAX105 Evaluation Kit Features ♦ Two Matched 6-Bit, 800 Msps ADCs ♦ 0.8Vp-p Input Signal Range ♦ Demultiplexed Differential LVDS Outputs ♦ Square-Pin Headers for Easy Connection of Logic Analyzer to Digital Outputs ♦ Four-layer PC Board with Separate Analog and