MASTER SLAVE COMMUNICATION Search Results

KEIL

Contextual Info: PSoC Creator Component Datasheet I2C Master/Multi-Master/Slave 3.30 Features • Industry-standard NXP® I2C bus interface • Supports slave, master, multi-master and multi-master-slave operation  Requires only two pins SDA and SCL to interface to I2C bus

Contextual Info: PSoC Creator Component Datasheet I2C Master/Multi-Master/Slave 3.10 Features • Industry-standard NXP® I2C bus interface • Supports slave, master, multi-master and multi-master-slave operation  Requires only two pins SDA and SCL to interface to I2C bus

Contextual Info: PSoC Creator Component Datasheet I2C Master/Multi-Master/Slave 3.0 Features • Industry-standard NXP® I2C bus interface • Supports Slave, Master, Multi-Master and Multi-Master-Slave operation  Only two pins SDA and SCL required to interface to I2C bus

Contextual Info: PSoC Creator Component Datasheet I2C Master/Multi-Master/Slave 3.20 Features • Industry-standard NXP® I2C bus interface • Supports slave, master, multi-master and multi-master-slave operation  Requires only two pins SDA and SCL to interface to I2C bus

Contextual Info: PSoC Creator Component Datasheet I2C Master/Multi-Master/Slave 3.1 Features • Industry-standard NXP® I2C bus interface • Supports slave, master, multi-master and multi-master-slave operation  Requires only two pins SDA and SCL to interface to I2C bus

Contextual Info: PSoC Creator Component Datasheet I2C Master/Multi-Master/Slave 2.20 Features • Industry standard Philips® I2C bus interface • Supports Slave, Master, Multi-Master and Multi-Master-Slave operation    Only two pins SDA and SCL required to interface to I 2C bus

RNW RESISTOR

Abstract: arbitrage verilog code for I2C MASTER
Contextual Info: PSoC Creator Component Data Sheet I2C Master/Multi-Master/Slave 2.10 Features • Industry standard Philips® I2C bus interface • Supports Slave, Master, Multi-Master and Multi-Master-Slave operation • Only two pins SDA and SCL required to interface to I2C bus

Contextual Info: PCI 9060SD MAY 1996 VERSION 0.6 PCI Bus Master Interface Chip for Master and Slave Adapters General Description _ Featu res_ • • PCI Specification 2.1 compliant PCI Bus Master Interface supporting master and slave adapters

megafunction

Abstract: EP3SE50 EP3C40-6 EP2C35-6
Contextual Info: Run-time programmable master or slave mode operation SPI_MS Serial Peripheral Interface Master/Slave Altera Megafunction High bit rates Bit rates generated in Master mode: ÷2, ÷4, ÷8, ÷10, ÷12, …, ÷512 of the system clock Bit rates supported in slave

87LCP764

Abstract: BCXA i2c software program master slave communication 87LPC764 AN430 AN435 AN463 AN464 87LPC76X
Contextual Info: INTEGRATED CIRCUITS ABSTRACT Presents short and simple I2C software routines that support only slave rather than master or master & slave operation and an ASM demonstration program. The slave-only software in this app note complements the master mode software presented in AN464, Using

87LPC764

Abstract: AN430 AN435 AN463 AN464 app abstract 87LCP764
Contextual Info: INTEGRATED CIRCUITS ABSTRACT Presents short and simple I2C software routines that support only slave rather than master or master & slave operation and an ASM demonstration program. The slave-only software in this app note complements the master mode software presented in AN464, Using

64x18 synchronous sram

Abstract: TSMC Flash interface VHDL code for slave SPI with FPGA TSMC embedded Flash rx data path interface in vhdl verilog code for slave SPI with FPGA TSMC Flash memory 0.18
Contextual Info: Run-time programmable master or slave mode operation SPI_MS Serial Peripheral Interface Master/Slave Core High bit rates Bit rates generated in Master mode: ÷2, ÷4, ÷8, ÷10, ÷12, …, ÷512 of the system clock Bit rates supported in slave mode: fSCK ≤ fSYSCLK ÷4

verilog code for slave SPI with FPGA

Abstract: XC3S50 XC2V80
Contextual Info: Run-time programmable master or slave mode operation SPI_MS Serial Peripheral Interface Master/Slave Xilinx Core High bit rates Bit rates generated in Master mode: ÷2, ÷4, ÷8, ÷10, ÷12, …, ÷512 of the system clock Bit rates supported in slave mode: fSCK ≤ fSYSCLK ÷4

transistor BC 550

Abstract: TRANSISTOR tr4 SP1670LC
Contextual Info: SP1670 MASTER/SLAVE TYPE D FLIP-FLOP The SP1670 is a D-type Master-Slave Flip-Flop designed for use in high speed digital applications. Master-slave construction renders the SP1670 relatively insensitive to the shape o f the clock waveform, since only the voltage levels at

Contextual Info: A PLESSEY W Solid State — SP16F70 MASTER/SLAVE The SP16F70 is a D-type Master-Slave Flip-Flop designed for use in high speed digital applications. Master-slave construction renders the SP16F70 relatively insensitive to the shape of the clock waveform, since only the voltage levels at

i2c master verilog code

Abstract: verilog code for i2c
Contextual Info: PSoC Creator Component Data Sheet I2C Master/Multi-Master/Slave 2.0 Features • Industry standard Philips® I2C bus compatible interface • Supports Slave, Master, and Multi-Master operation • Only two pins sda and scl required to interface to I2C bus

TN261

Contextual Info: TN261 The Slave Port Driver The Rabbit family of microprocessors has hardware for a slave port, allowing a master controller to read and write certain internal registers on the Rabbit. The library, Slaveport.lib, implements a complete master/slave protocol for the Rabbit slave port. Sample libraries, Master_serial.lib and

TR26

Abstract: SP16F
Contextual Info: PLESSEY SEMICONDUCTORS TS dË J 7S5GS13 DD0b7flfl □ 95D 06788 7220513 PLESSEY SEMICONDUCTORS D T 'f t '0 7 'ô J r PLESSEY S em ico n d u cto rs. SP1670 MASTER/SLAVE TYPE D FLIP-FLOP The SP1670 is a D-type Master-Slave Flip-Flop designed for use in high speed digital applications. Master-slave

F07A

Contextual Info: APPLICATION NOTE H8/38076R Master-Slave Communication Using I2C Clock-Synchronous Serial Format Introduction In this example the I2C2 Inter IC Bus Interface 2 module of the H8/38076R is used for master-slave communication in I2C clock-synchronous serial format.

AVR32105

Abstract: AP7000 AVR32 AVR32101 STK1000
Contextual Info: AVR32105: Master and Slave SPI Driver Features - Four chip selects with external decoder support allow communication with up to 15 peripherals - Four chip select registers allowing up to four different slave setups in master mode - Supports a wide range of devices

Contextual Info: DeviceNet Slave / Modbus Master Gateway GW-7243D The GW-7243D is one of DeviceNet products in ICP DAS and it stands as a DeviceNet slave to Modbus TCP/RTU/ASCII master gateway device. It allows a master located on a DeviceNet network to enter a dialogue with slave devices on the Modbus TCP/RTU/ASCII network. In DeviceNet network, it

TRANSISTOR tr4

Abstract: SP1670 SP1670DG SP1670LC TR23 LC20 TR22
Contextual Info: A FLESSEY W S e m ic o n d u c to rs SP1670 MASTER/SLAVE TYPE D FLIP-FLOP The SP1670 is a D-type Master-Slave Flip-Flop designed for use in high speed digital applications. Master-slave construction renders the SP1670 relatively insensitive to the shape o f the clock waveform, since only the voltage levels at

AVR32105

Abstract: spi slave AVR32 STK1000 Spirea Atmel AVR32 AVR32101 SPI DRIVER AP7000 AVR32
Contextual Info: AVR32105: Master and Slave SPI Driver Features - Four chip selects with external decoder support allow communication with up to 15 peripherals - Four chip select registers allowing up to four different slave setups in master mode - Supports a wide range of devices

master-slave 8051

Abstract: LF30CV SST25VF010 SST25VF020 F2051 FLASHFLEX51 memory chip microcontroller schematic
Contextual Info: FlashFlex51 Microcontroller Single Master, Multi-Slave Serial Peripheral Interface Application Note June 2003 FlashFlex51 MCU: Single Master, Multi-Slave Serial Peripheral Interface 1.0 INTRODUCTION 2.0 HARDWARE The SPI protocol is a widely accepted and easily used