SN74ACT7804
Abstract: SN74ACT7806 SN74ACT7814 64X18
Text: SN74ACT7814 64x18 STROBED FIRST-IN, FIRST-OUT MEMORY S C A S 2 0 9 A -A P R IL 1 9 9 2 - R EVISED SEPTE M B E R 1995 Member of the Texas Instruments Widebus Family DL PACKAGE TOP VIEW Load Clock and Unload Clock Can Be Asynchronous or Coincident RESET [ 1
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SN74ACT7814
64x18
SCAS209A
50-pF
SN74ACT7804
SN74ACT7806
300-mil
25-mil
SN74ACT7806
SN74ACT7814
64X18
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Untitled
Abstract: No abstract text available
Text: SN74ACT781 4 64x18 STROBED FIRST-IN, FIRST-OUT M EM OR Y S C AS 209A - APRIL 1992 - REVISED SEPTEMBER 1995 M e m b e r of the Te x a s I n s t r u m e n t s W i d e b u s Fa mi l y DL PACKAGE TO P V IE W Load Cl o c k and Unl oa d Cl ock Can Be A s y n c h r o n o u s or C o i n c i d e n t
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SN74ACT781
64x18
SN74ACT7806
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ad 161
Abstract: vhdl code PN code generator ad 152 transistor ad 153 transistor S-108 PF144 PQ208 QL5130 QL5130-33APF144C QL5130-33APQ208C
Text: QL5130 - QuickPCITM 33 MHz/32-bit PCI Target with Embedded Programmable Logic and Dual Port SRAM last updated 12/1099 Device Highlights DEVICE HIGHLIGHTS Q8DÃ7ñÃ""ÃHCÃ"!ÃivÃqhhÃhqÃhqq
r High Performance PCI Controller • 32-bit / 33 MHz PCI Target
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QL5130
Hz/32-bit
32-bit
95/98/Win
ad 161
vhdl code PN code generator
ad 152 transistor
ad 153 transistor
S-108
PF144
PQ208
QL5130-33APF144C
QL5130-33APQ208C
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SN74ACT7803
Abstract: SN74ACT7805 SN74ACT7813 SN74ALVC7803 SN74ALVC7805 SN74ALVC7813
Text: SN74ALVC7803, SN74ALVC7805, SN74ALVC7813 512x 18, 256x 18, 64x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORIES SCAS436 - JUNE 1994 DL PACKAGE TOP VIEW Free-Running Read and Write Clocks Can Be Asynchronous or Coincident RESET D17 D16 D15 D14 D13 D12 D11 Read and Write Operations Synchronized to
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SN74ALVC7803,
SN74ALVC7805,
SN74ALVC7813
SCAS436
50-pF
SN74ACT7803,
SN74ACT7805
SN74ACT7813
D1D1D13
SN74ACT7803
SN74ACT7813
SN74ALVC7803
SN74ALVC7805
SN74ALVC7813
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Untitled
Abstract: No abstract text available
Text: Aluminum Electrolytic Capacitors Large Can Type GUP Series GUP Series Features • High C V value with expanded case size <>64 x 103 - <|>90 x 221 ■ High ripple current (approx. 1 . 5 - 2 times of GYU-series) Specifications Item Performance Characteristics
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120Hz,
120Hz/
64x121
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verilog code for slave SPI with FPGA
Abstract: XC3S50 XC2V80
Text: Run-time programmable master or slave mode operation SPI_MS Serial Peripheral Interface Master/Slave Xilinx Core High bit rates Bit rates generated in Master mode: ÷2, ÷4, ÷8, ÷10, ÷12, …, ÷512 of the system clock Bit rates supported in slave mode: fSCK ≤ fSYSCLK ÷4
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64x18
XC3S50-5
XC3S100E-5
XC2V80-6
XC4VLX15-12
XC5VLX30-3
verilog code for slave SPI with FPGA
XC3S50
XC2V80
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QL5332-33APQ208C
Abstract: 1.9 TDI Schematic PB256 PCI32 PQ208 QL5032 QL5332 PCI32N AD1892
Text: QL5332 - Enhanced QuickPCITM Device 33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM last updated 2/5/01 QL5332 - Enhanced QL5032 • ■ ■ ■ ■ ■ ■ PCI Bus – 33 MHz 32 bits data and address Supports all PCI commands (including configuration
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QL5332
Hz/32-bit
QL5032
QL5332-33APQ208C
1.9 TDI Schematic
PB256
PCI32
PQ208
QL5032
PCI32N
AD1892
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ST CHN t4
Abstract: No abstract text available
Text: QL5064 QuickPCI Data Sheet •••••• 66 MHz/64-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM Device Highlights High Performance PCI Controller • 64-bit/66 MHz Master/Target PCI Controller automatically backwards compatible to 33 MHz
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QL5064
Hz/64-bit
64-bit/66
32-bits)
64-bit
busses/100
ST CHN t4
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Untitled
Abstract: No abstract text available
Text: QL5064 QuickPCI Data Sheet •••••• 66 MHz/64-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM Device Highlights High Performance PCI Controller • 64-bit/66 MHz Master/Target PCI Controller automatically backwards compatible to 33 MHz
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QL5064
Hz/64-bit
64-bit/66
32-bits)
64-bit
busses/100
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Untitled
Abstract: No abstract text available
Text: Am 29332 32-Bit Arithmetic Logic Unit • Single Chip, 32-Bit ALU Supports 8 0 -9 0 ns m icrocycle tim e fo r the 32-bit data path. It is a com binatorial ALU with equal cy cle tim e fo r all instructions. Flow -through A rchitecture A com binatorial ALU with tw o input data ports and
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32-Bit
32-bit
WF023691
Y0-Y31
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67417J
Abstract: 128X9 PIS01 serial input parallel output
Text: Serializing First-In-First-O ut FIFO 6 4 x 8 /9 Memory Features/ Benefits • High-speed 28-MHz serial shift-ln/shift-out rate • 10-MHz parallel shift-in/shift-out rate • Three-state outputs with Hi-current drive 67417 Ordering Information PART NUMBER
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64x8/9
28-MHz
10-MHz
PIS01)
SIP01
67417J
128X9
PIS01
serial input parallel output
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Untitled
Abstract: No abstract text available
Text: Order this data sheet by H4C/D MOTOROLA H SEMICONDUCTOR “ TECHNICAL DATA Advance Information H4C SERIES CMOS ARRAYS and the CDA™ ARCHITECTURE H IG H P ER FO R M A NC E T R IP L E LAYER M ETAL S U B -M IC R O N CMOS ARRAYS The s u b -m ic ro n H 4C S e rie s ’ " CM OS gate array fa m ily and th e new
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PF144
Abstract: QL5030
Text: Back QL5030 - QuickPCI ESP 33 MHz/32-bit PCI Target with Embedded Programmable Logic and Dual Port SRAM Advance Data DEVICE HIGHLIGHTS Updated: 22-Feb-99 High Performance PCI Controller - 32-bit / 33 MHz PCI Target PCI Zero-wait state PCI Target provides 132 MB/s transfer rates
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QL5030
Hz/32-bit
22-Feb-99
32-bit
95/98/NT4
PF144
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Untitled
Abstract: No abstract text available
Text: a CtT7A i T O ' 41 Serializing First-In First-Out (FIFO 64 x 8/9 Memory Features/Benefits • High-speed 28-MHz serial shlft-ln/shilt-out rate Advanced Micro Devices Ordering Information • 10-MHz parallel shlit-ln/shlft-out rate Part Number Package Temp
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28-MHz
10-MHz
64x8/9
PIS01
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Untitled
Abstract: No abstract text available
Text: 大型铝电解电容器 LSG LARGE CAN TYPE ALUMINUM ELECTROLYTIC CAPACITORS 系列 LSG SERIES 螺栓端子型105℃ 5000小时品 105℃ 5000 hours, Screw Terminal Type ◆特 长／FEATURES • 105℃5000小时品。 • RoHS指令对应品。 Load Life : 105℃ 5000 hours.
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50450V
20120Hz)
120Hz
/120Hz
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Untitled
Abstract: No abstract text available
Text: LSG LARGE CAN TYPE ALUMINUM ELECTROLYTIC CAPACITORS LSG SERIES 105℃ 5000 hours, Screw Terminal Type ◆FEATURES ・Load Life : 105℃ 5000 hours. ・RoHS compliance. ◆SPECIFICATIONS Items Characteristics Category Temperature Range −25~＋105℃ Rated Voltage Range
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50450V
120Hz
/120Hz,
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hct 4047 bt
Abstract: SN74ALS679 FCT Fast CMOS TTL Logic 74LS 4075 7804 inverter SN74368A DTL Logic 4069 CMOS hex inverter SN502 CD74AC374
Text: IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold
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SDYZ001A,
SN74LS138D
SN74LS138DR
SN74LS138N
SN74LS138N3
SN74LS138NSR
images/sn74ls138
hct 4047 bt
SN74ALS679
FCT Fast CMOS TTL Logic
74LS 4075
7804 inverter
SN74368A
DTL Logic
4069 CMOS hex inverter
SN502
CD74AC374
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74HCT 4013
Abstract: CD4078 4093 BF SN74368A SN74ALS679 LXZ Series 4069 CMOS hex inverter 2a2 vacuum tube CD74AC374 cd408
Text: SN54HC240, SN74HC240 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SCLS128B – DECEMBER 1982 – REVISED MAY 1997 D D SN54HC240 . . . J OR W PACKAGE SN74HC240 . . . DW OR N PACKAGE TOP VIEW 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers
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SN54HC240,
SN74HC240
SCLS128B
300-mil
SN54HC240
SN74HC240
HC240
SDYZ001A,
SN74HC240DW
SN74HC240DWR
74HCT 4013
CD4078
4093 BF
SN74368A
SN74ALS679
LXZ Series
4069 CMOS hex inverter
2a2 vacuum tube
CD74AC374
cd408
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PF144
Abstract: QL5030 QL5030-33APF144C TQ144
Text: QL5030 QuickPCI Data Sheet • • • • • • 33 MHz/32-bit PCI Target with Embedded Programmable Logic and Dual Port SRAM 1.0 Device Highlights High Performance PCI Controller • Programmable Interrupt Generator • I2O Support with Local Processor
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QL5030
Hz/32-bit
32-bit
95/98/Win
2000/NT4
PF144
QL5030-33APF144C
TQ144
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450WV
Abstract: No abstract text available
Text: 大形アルミニウム電解コンデンサ LSG LARGE CAN TYPE ALUMINUM ELECTROLYTIC CAPACITORS LSG シリーズ SERIES ネジ端子形105℃標準品 105℃ Standard, Screw Terminal Type ◆特 長／FEATURES ・RoHS指令対応品。 RoHS compliance.
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50450V
120Hz
/120Hz,
450WV
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M2GL005
Abstract: db hpms
Text: Revision 0 IGLOO2 FPGAs Introduction Microsemi’s IGLOO 2 FPGAs integrate fourth generation flash-based FPGA fabric and high performance communications interfaces on a single chip. The IGLOO2 family is the industry’s lowest power, most reliable, and the most secure programmable logic solution. This next generation IGLOO2
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QL5130-33APF144C
Abstract: QL5130 QL5130-33APQ208C QL5130-33APQ
Text: QL5130 QuickPCI Data Sheet • • • • • • 33 MHz/32-Bit PCI Target with Embedded Programmable Logic and Dual Port SRAM Device Highlights High Performance PCI Controller Programmable Logic • 57 K system gates/619 logic cells • 13,824 RAM bits, up to 157 I/O pins
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QL5130
Hz/32-Bit
gates/619
32-bit/33
16-bit
64-deep
128-deep
QL5130-33APF144C
QL5130-33APQ208C
QL5130-33APQ
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Untitled
Abstract: No abstract text available
Text: QL5030 - QuickPCI ESP 33 MHz/32-bit PCI Target with Embedded Programmable Logic and Dual Port SRAM Advance Data D e v ic e H ig h l ig h t s Updated: 1-Apr-99 5 High Performance PCI Controller - 32-bit / 33 M Hz PCI Target PCI Zero-wait state PCI Target provides 132 MB/s transfer rates
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QL5030
Hz/32-bit
1-Apr-99
32-bit
95/98/NT4
PCI32T
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PDF
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MCR 22-8 transistor power
Abstract: Transistor motorola 418 10146 1987 carrier A022H on 5295 equivalents HDC031 Mustang 300 HDC011 HDC016 HDC049
Text: Order this data sheet by HDC/D MOTOROLA SEMICONDUCTOR TECHNICAL DATA HIGH PERFORMANCE TRIPLE LAYER METAL HDC SERIES CMOS ARRAYS 1.0 MICRON CMOS ARRAYS Built on a 1.0 micron, triple-layer metal CMOS process, the HDC Series represents a significant advancement in microchip technology.
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