Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    MACROCELL Search Results

    MACROCELL Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    cypress flash 370

    Abstract: logic block diagram of cypress flash 370 device 22v10 CY7C375 FLASH370 o112i cypress flash 370 CPLD cypress flash 370 device technology
    Text: fax id: 6130 For new designs see CY7C375i CY7C375 UltraLogic 128-Macrocell Flash CPLD Features Functional Description • 28 macrocells in eight logic blocks • 28 I/O pins • 6 dedicated inputs including 4 clock pins • Bus Hold capabilities on all I/Os and dedicated inputs


    Original     		CY7C375i CY7C375 128-Macrocell CY7C375 LASH370TM FLASH370 22V10 I/O112-I/O127 cypress flash 370 logic block diagram of cypress flash 370 device o112i cypress flash 370 CPLD cypress flash 370 device technology PDF

    ATV2500BQ

    Abstract: ATV2500B ATV2500BL ATV2500BQL
    Text: Features • High Performance, High Density Programmable Logic Device – Typical 7 ns Pin-to-Pin Delay – Fully Connected Logic Array With 416 Product Terms • Flexible Output Macrocell – 48 Flip-Flops - Two per Macrocell – 72 Sum Terms – All Flip-Flops, I/O Pins Feed In Independently


    Original     		ATV2500B ATV2500BQ ATV2500BL ATV2500BQL I/O17 I/O16 I/O15 I/O14 I/O13 I/O12 ATV2500BQ ATV2500B ATV2500BL ATV2500BQL PDF

    XC9572

    Abstract: XC9572-10PC44C xc9572-15PQ100 15PC44I xc9572 data sheet XC9572-7PC44C PC44 PC84 xc9572-10pq100c XC9572-15PC84C
    Text: XC9572 In-System Programmable CPLD R DS065 v4.2 April 15, 2005 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 72 macrocells with 1,600 usable gates Up to 72 user I/O pins 5V in-system programmable


    Original     		XC9572 DS065 36V18 XC9572-10PC44C xc9572-15PQ100 15PC44I xc9572 data sheet XC9572-7PC44C PC44 PC84 xc9572-10pq100c XC9572-15PC84C PDF

    7C344-25

    Abstract: C344 74HC CY7C344 Signal Path Designer C3445
    Text: CY7C344 32-Macrocell MAX EPLD Features tional I/O pins communicate to one logic array block. In the CY7C344 LAB there are 32 macrocells and 64 expander product terms. When an I/O macrocell is used as an input, two expanders are used to create an input path. Even if all of the


    Original     		CY7C344 32-Macrocell CY7C344 28-pin, 300-mil 28-pin 7C344-25 C344 74HC Signal Path Designer C3445 PDF

    XCR3128XL-10VQ100I

    Abstract: XCR3128XL-10TQ144I XCR3128XL-7CS144I XCR3128XL XCR3128XL-10CS144I XCR3128XL-10VQ100C CS144 marking E13 diode L12M1 k3296
    Text: R XCR3128XL 128 Macrocell CPLD DS016 v2.1 August 21, 2003 14 Preliminary Product Specification Features Description • Low power 3.3V 128 macrocell CPLD • 6.0 ns pin-to-pin logic delays • System frequencies up to 175 MHz • 128 macrocells with 3,000 usable gates


    Original     		XCR3128XL DS016 144-pin 144-ball 100-pin XCR3128XL-10VQ100I XCR3128XL-10TQ144I XCR3128XL-7CS144I XCR3128XL-10CS144I XCR3128XL-10VQ100C CS144 marking E13 diode L12M1 k3296 PDF

    PT80

    Abstract: No abstract text available
    Text: ispLSI 81080V Features Functional Block Diagram • SuperBIG HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 3.3V Power Supply — 60,000 PLD Gates/1080 Macrocells — 192-360 I/O Pins Supporting 3.3V/2.5V I/O — 1440 Registers — High-Speed Global and Big Fast Megablock BFM


    Original     		1080V Gates/1080 20-Macrocell 492-Ball 0212/81080V 1080V-125LB272 272-Ball 1080V-125LB492 1080V-90LB272 PT80 PDF

    XCR5128

    Abstract: MC16 XCR3128 Xilinx XCR5128 P-QFP40
    Text: APPLICATION NOTE This product has been discontinued. Please see www.xilinx.com/partinfo/notify/pdn0007.htm for details. R DS041 v1.4 January 19, 2001 XCR5128: 128 Macrocell CPLD 14* Product Specification Features Description • The XCR5128 CPLD (Complex Programmable Logic


    Original     		com/partinfo/notify/pdn0007 DS041 XCR5128: XCR5128 100-pin VQ100: TQ128: 128-pin MC16 XCR3128 Xilinx XCR5128 P-QFP40 PDF

    MACH130-20

    Abstract: MACH130 MACH230 PAL22V10 PAL26V16
    Text: FINAL COM’L: -15/20 IND: -18/24 MACH130-15/20 Lattice Semiconductor High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS 84 Pins 64 Outputs 64 Macrocells 64 Flip-flops; 4 clock choices 15 ns tPD Commercial 18 ns tPD Industrial 4 “PAL26V16” Blocks


    Original     		MACH130-15/20 PAL26V16" MACH131, MACH230, MACH231, MACH435 MACH130 PAL22V10 14131H-26 MACH130-20 MACH230 PAL26V16 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C371i UltraLogic 32-Macrocell Flash CPLD Features signed to bring the ease of use and high performance of the 22V10, as well as PCI Local Bus Specification support, to high-density CPLDs. • • • • 32 macrocells in two logic blocks 32 I/O pins


    Original     		CY7C371i 32-Macrocell 22V10, FLASH370i PDF

    XC95144XL-10TQ144I

    Abstract: XC95144XL-10TQG100C XAPP114 XAPP427 XC9500XL XC95144 XC95144XL XC95144XL-5-CS144 XC95144XL-5TQ100 xc95144xl tq144
    Text: XC95144XL High Performance CPLD R DS056 v1.8 July 15, 2005 5 Product Specification Features Power Estimation • • • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell


    Original     		XC95144XL DS056 XC9500XL CS144 220oC. XC95144XL-10TQ144I XC95144XL-10TQG100C XAPP114 XAPP427 XC95144 XC95144XL-5-CS144 XC95144XL-5TQ100 xc95144xl tq144 PDF

    PAL26V12

    Abstract: MACH120 MACH220 PAL22V10
    Text: FINAL COM’L: -10/12/15/20 IND: -14/18/24 MACH220-10/12/15/20 Lattice Semiconductor High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS 68 Pins 48 Outputs 96 Macrocells 96 Flip-flops; 4 clock choices 10 ns tPD 8 “PAL26V12” blocks with buried macrocells


    Original     		MACH220-10/12/15/20 PAL26V12" MACH120 MACH221 MACH220 PAL22V10 14130I-26 14130I-27 PAL26V12 PDF

    20RA10

    Abstract: 20RA10-15 PLDC20RA10 PLDC20RA10-15JC RA1021
    Text: fax id: 6015 1P LDC20 RA10 PLDC20RA10 Reprogrammable Asynchronous CMOS Logic Device Features • • • • • • • • • — ICC max = 85 mA Military • High reliability — Proven EPROM technology Advanced-user programmable macrocell CMOS EPROM technology for reprogrammability


    Original     		LDC20 PLDC20RA10 20RA10 20RA10-15 PLDC20RA10 PLDC20RA10-15JC RA1021 PDF

    62A17

    Abstract: HCA62A17 62A50 18PDIP 68-LCC
    Text: í Order this data sheet by HCA62A00/D M MOTOROLA HCA62A00 Series SEM ICO NDUCTO RS P.O B O X 20912 • PHOENIX, A R IZ O N A 85036 HCA62A00 SERIES CMOS MACROCELL ARRAYS The HCA62A00 series m acrocell arrays are im plem ented in sil­ icon gate, 2-m icron draw n gate length, dual-layer metal intercon­


    OCR Scan     		HCA62A00/D HCA62A00 62A17 HCA62A17 62A50 18PDIP 68-LCC PDF

    vp44

    Abstract: CY37064 CY37064V
    Text: «oaHaoooiMMMWfMMMMMM!9:^ v’*'» -^ jjÉBT * ¿f5 ’00“’'* '^ 7“T{• < 1; .r - - •■■■■■■ c PRELIMINARY CY37064V 3, £ ,.* k v / k J UltraLogic 3.3V 64-Macrocell ISR™CLPD — tPD = 8.5ns Features — ts = 5.0 ns • 64 macrocells in four logic blocks


    OCR Scan     		CY37064V 64-Macrocell vp44 CY37064 CY37064V PDF

    84 PIN CERAMIC QUAD FLAT PACK

    Abstract: 2600 corning cypress flash 370 7C374-100 7C374-66 7C374L-66 CY7C373 CY7C374 FLASH370 CY7C374-83GC
    Text: fax id: 6129 —— — - = : ! W Æ j r I 1 CY7C374 17 Q Q IT C O O UltraLogic 128-Macrocell Flash CPLD Features The logic blocks in the FLASH370 architecture are connected with an extremely fast and predictable routing resource— the Programmable Interconnect Matrix PIM . The PIM brings flex­


    OCR Scan     		CY7C374 128-Macrocell 84-pin 100-pin CY7C373 CY7C374 ASH370t FLASH370 84 PIN CERAMIC QUAD FLAT PACK 2600 corning cypress flash 370 7C374-100 7C374-66 7C374L-66 CY7C374-83GC PDF

    31-oq

    Abstract: 7C342-25 CY7C342-35HMB 7C342-35 CY7C342 CY7C342B OQ11
    Text: CY7C342 CY7C342B rif CYPRESS 128-Macrocell M AX EPLD Features Functional Description • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology CY7C342


    OCR Scan     		CY7C342 CY7C342B 128-Macrocell CY7C342) 65-micron CY7C342B) 68-pin CY7C342/CY7C342B CY7C342/ CY7C342B 31-oq 7C342-25 CY7C342-35HMB 7C342-35 OQ11 PDF

    CY37384

    Abstract: CY37384V L0651
    Text: = j— PRELIMINARY T. # CY37384V UltraLogic 3.3V 384-Macrocell ISR™ CPLD Fully Routable with 100% Logic Utilization Features — JTAG-compliant on-board programming The CY37384V is designed with a robust routing architecture which allows utilization of the entire device with a fixed pinout.


    OCR Scan     		CY37384V 384-Macrocell CY37384 CY37384V L0651 PDF

    PAL26V16

    Abstract: teradyne lasar
    Text: FINAL COM’L: -15/20 IND: -18/24 Z I Advanced Micro Devices M A C H 1 3 0 - 1 5 /2 0 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 84 Pins ■ 64 Outputs ■ 64 Macrocells ■ 64 Flip-flops; 4 clock choices ■ 15 ns tpD Commercial


    OCR Scan     		PAL26V16" MACH131, MACH230, MACH231, MACH435 MACH130 PAL22V10 MACH130-15/20 55755b PAL26V16 teradyne lasar PDF

    EPLD 5128

    Abstract: EPM5128-1 K942
    Text: EPM5128 EPLD Features □ □ □ □ □ H igh-density, 128-macrocell, general-purpose MAX 5000 EPLD High-speed multi-LAB architecture t PD as fast as 25 ns Counter frequencies up to 50 MHz Pipelined data rates up to 62.5 MHz 256 shareable expander product terms "expanders" allowing over


    OCR Scan     		EPM5128 128-macrocell, 68-pin ALTED001 EPLD 5128 EPM5128-1 K942 PDF

    PAL10H20EV8

    Abstract: No abstract text available
    Text: PALI 0H20EV8-6/PAL10020EV8-6 Advanced Micro Devices ECL Registered Programmable Array Logic DISTINCTIVE CHARACTERISTICS High-performance; tpo “ 6 ns, fjviAX * 125 MHz Eight user-programmable output logic macrocells for registered or combinatorial operation


    OCR Scan     		0H20EV8-6/PAL10020EV8-6 PAL10H20EG8 PAL10020EG8 C-017A WF026070 PAL10H20EV8 PDF

    EPM5130

    Abstract: 100-Pin Package Pin-Out Diagram D2-3401 EPM 5130
    Text: EPM5130 EPLD □ □ Features □ □ □ □ □ □ □ High-density, 128-macrocell, general-purpose MAX 5000 EPLD 128 m acrocells optim ized for pin-intensive applications, easily integrating over 60 TTL MSI and SSI components High-speed multi-LAB architecture


    OCR Scan     		EPM5130 128-macrocell, 32-bit 16-bit 100-pin 84-pin in100-Pin ALTED001 100-Pin Package Pin-Out Diagram D2-3401 EPM 5130 PDF

    Untitled

    Abstract: No abstract text available
    Text: COM’L :-7/10/15 a MIL: -12/20 Advanced Micro Devices PAL22V10 Family, AmPAL22V10/A 24-Pin TTL Versatile PAL Device DISTINCTIVE CHARACTERISTICS • As fast as 7.5 ns propagation delay and 91 MHz fMAx external ■ 10 Macrocells programmable as registered or


    OCR Scan     		PAL22V10 AmPAL22V10/A 24-Pin 28-pin 16559B-16 PDF

    EP910T

    Abstract: altera EP910 EP910-T
    Text: EP910T EPLD Features □ □ a □ □ High-performance, 24-macrocell Classic EPLD Combinatorial speeds with tPD = 30 ns Counter frequencies up to 33 MHz Pipelined data rates up to 41 MHz Programmable I/O architecture with up to 36 inputs or 24 outputs Pin-, function-, and programming file-compatible with Altera's EP910


    OCR Scan     		EP910T 24-macrocell EP910 EP910A 44-pin 40-pin ALTED001 altera EP910 EP910-T PDF

    EP1810-35T

    Abstract: ALTERA EP altera EP1810
    Text: Features □ □ □ □ □ □ High-performance, 48-macrocell Classic EPLD Combinatorial speeds with tPD = 20 ns, 25 ns, and 35 ns - Counter frequencies up to 50 MHz Pipelined data rates up to 62.5 MHz Programmable I/O architecture with up to 64 inputs or 48 outputs


    OCR Scan     		48-macrocell EP1810 MIL-STD-883-compliant 68-pin EP1810T EP1810-20T, EP1810-25T, EP1810-35T ALTED001 ALTERA EP altera EP1810 PDF