M80C1 Search Results

m8087 intel

Contextual Info: p R iy iM O B y w in te i M80C187 80-BIT NUMERIC PROCESSOR EXTENSION Military High Perform ance 80-Bit Internal Architecture Tw o to Three Tim es M8087 Perform ance at Equivalent Clock Speed Im plements A N S I/IE E E Standard 7541985 fo r Binary Floating-Point

Contextual Info: i i r t r J Ä i M @ l O M IF C O M A Y O !* ] M80C186XL20,16,12,10 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR Low Power, Full Static Version of M80C186 Operation Modes: — Enhanced Mode — DRAM Refresh Control Unit — Power-Save Mode — Direct Interface to 80C187

D1515

Abstract: Q1515 80c196 instruction intel 80c196 opcode sheet MTO spco
Contextual Info: PftSUBflO INM V M80C196KB 16-BIT HIGH PERFORMANCE CHMOS MICROCONTROLLER Military • 232 Byte Register File ■ Register-to-Register Architecture ■ 28 Interrupt Sources/16 Vectors ■ 2.3 us 16 x 16 Multiply 12 MHz ■ 4.0 us 32/16 Divide (12 MHz) ■ Powerdown and Idle Modes

JS4041

Abstract: 1nt08 M80C198KB h jst 03 intel 8096 assembly language 271060 271069 271088 CQFP24
Contextual Info: in t e i M80C196KB 16-BIT HIGH PERFORMANCE CHMOS MICROCONTROLLER M ilitary 232 B y te R e g is te r F ile • R e g is te r-to -R e g is te r A rc h ite c tu re ■ 28 In te rru p t S o u rc e s /1 6 V e c to rs F u ll D u p lex S e ria l P o rt H igh S peed I/O S u b syste m

SAL 41B

Abstract: 8088 instruction set CTX 12S RD smd lm 398- SAMPLE AND HOLD
Contextual Info: Ä in te i I M K l l O M I F iO M A T O ! * ! M80C186XL20,16,12,10 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR • Low Power, Full Static Version of M80C186 ■ Operation Modes: — Enhanced Mode — DRAM Refresh Control Unit — Power-Save Mode — Direct Interface to 80C187

mg80c186

Abstract: 523ap order 231369 M801 80C186EB
Contextual Info: in te i M80C186EB-16, -13, -8 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR • Full Static Operation • True CMOS Inputs and Outputs • —55°C to + 125°C Operating Temperature Range • Integrated Feature Set — Low-Power Static CPU Core — Two Independent UARTs each with

M801

Abstract: M80C186
Contextual Info: M80C186 CHMOS HIGH INTEGRATION 16-BIT MICROPROCESSOR M ilitary • Direct Addressing Capability to 1 Mbyte and 64 Kbyte I/O ■ Operation Modes Include: — Enhanced Mode Which Has — DRAM Refresh — Power-Save Logic — Direct Interface to New CMOS Numerics Coprocessor

M8096

Abstract: 80C196 assembly language 16 bit 8096 microcontroller architecture hil 518-5 intel 80c196 opcode sheet M80C196KB 8096 microcontroller features 80C196 mnemonic intel 8096 instruction set intel 80c196 INSTRUCTION SET
Contextual Info: OMF fößMT!l IM M80C196KB 16-BIT HIGH PERFORMANCE CHMOS MICROCONTROLLER Military • ■ ■ ■ ■ ■ ■ ■ ■ 232 Byte Register File Register-to-Register Architecture 28 Interrupt Sources/16 Vectors 2.3 jus 16 x 16 Multiply 12 MHz 4.0 ju.s 32/16 Divide (12 MHz)

Contextual Info: M80C186EB ERRATA REVISION HISTORY The current stepping B step of the M 80C186EB has the following known functional anomaly. The first revision of this data sheet (271214-001) in­ dicated only 8 MH z and 13 M H z availability. The M 80C 186EB will also be available in a 16 M H z ver­

Fortran-86

Abstract: intel 8088 memory 8088 instruction set intel 80186 memory map 80C186XL 80c187
Contextual Info: in te i Ä W Ä l O N IP Q IR G M irO lD N M80C186XL20,16,12,10 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR Low Power, Full Static Version of M80C186 Operation Modes: — Enhanced Mode — DRAM Refresh Control Unit — Power-Save Mode — Direct Interface to 80C187

001100dw

Contextual Info: M80C186EB INSTRUCTION SET SUMMARY Clock C yd— Format Comments DATA TRANSFER MOV = Move: Register to Register/Memory 1 0 0 Q1 QOw mod reg r/m 2/12 Register/memory to register 1000101w mod reg r/m 2/9 Immediate to register/memory 1 10001 1w mod 000 r/m data

ocs4

Contextual Info: M80C186EB PACKAGE INFORMATION This section describes the pins, pinouts, and thermal characteristics for the M80C186EB PGA package. For complete package specifications and informa­ tion, see the Intel Packaging Outlines and Dimen­ sions Guide Order Number: 231369 .

Contextual Info: P H iy fiflD iw M n f in t e i M80C196KB 16-BIT HIGH PERFORMANCE CHMOS MICROCONTROLLER Military 232 Byte Register File Register-to-Reglster Architecture 28 Interrupt Sources/16 Vectors 2.3 jus 16 x 16 Multiply 12 MHz 4.0 (is 32/16 Divide (12 MHz) Powerdown and Idle Modes

Contextual Info: irrte! p f ö iy t M Ä f M80C196KB 16-BIT HIGH PERFORMANCE CHMOS MICROCONTROLLER Military • 232 Byte Register File ■ Register-to-Register Architecture ■ ■ ■ ■ ■ ■ ■ 28 Interrupt Sources/16 Vectors 2.3 jits 16 x 16 Multiply 12 MHz 4.0 ju-s 32/16 Divide (12 MHz)

MG80C186

Abstract: TRANSISTOR IFW 82 MG80C 27121 MG80C186EB
Contextual Info: M SM AGM &E O M F@ ^R M Y O M in te i M80C186EB-16, -13, -8 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR • Full Static Operation • True CMOS Inputs and Outputs • - 55°C to + 125°C Operating Temperature Range Integrated Feature Set — Low-Power Static CPU Core

Contextual Info: M80C186EB BUS CYCLE WAVEFORMS Figures 19 through 25 present the various bus cy­ cles that are generated by the M80C186EB. What is shown in the figure is the relationship of the various bus signals to CLKOUT. These figures along with the information present in AC Specifications allow

M80C188

Abstract: UPPER10 GCS2
Contextual Info: M80C186EB INTRODUCTION The M80C186EB is the first product in a new gener­ ation of low-power, high-integration microproces­ sors. It enhances the existing 186 family by offering new features and new operating modes. The M80C186EB is object code compatible with the

MG80C186

Abstract: MG80C186EB M80C186 80C186EB
Contextual Info: intei M80C186EB-16,-13, -8 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR • Full Static Operation • True CMOS Inputs and Outputs • -55°C to + 125°C Operating Temperature Range • Integrated Feature Set — Low-Power Static CPU Core — Two Independent UARTs each with

Contextual Info: M80C186EB 88-LEAD CERAMIC PIN GRID ARRAY PACKAGE SEATINGPLANE A It il SEATING— H PLANE r=- e, 0 6 ALL PINS SWAGGED PIN DETAIL A,—* BASE — PLANE 271 214-33 Family: Ceramic Pin Grid Array Package Symbol Millimeters Inches Min Max Notes A 3.56 4.57 Ai

Contextual Info: P iiy iM O I M O W I M80C187 80-BIT NUMERIC PROCESSOR EXTENSION M ilitary m High Performance 80-Bit Internal Architecture • Two to Three Times M8087 Performance at Equivalent Clock Speed ■ Implements ANSI/IEEE Standard 7541985 for Binary Floating-Point

Contextual Info: P R E IL O B S IO K IM V in te i M80C187 80-BIT NUMERIC PROCESSOR EXTENSION M ilitary • High Performance 80-Bit Internai Architecture ■ Two to Three Times M8087 Performance at Equivalent Clock Speed ■ Implements ANSI/IEEE Standard 7541985 for Binary Floating-Point

MG80C186EB

Abstract: mg80c186
Contextual Info: M80C186EB M80C186EB PINOUT Table 5 lists the M 8 0C 186E B pin names with package location for the 88-Lead Pin Grid Array PGA component. Figure 8 depicts the complete M 8 0C 186E B pinout as viewed from the bottom side of the component, Table 5. MG80C186EB Pin Assignm ents

Contextual Info: M80C186EB RESET The M80C186EB will perform a reset operation any time the RESIN pin active. The RESIN pin Is actually synchronized before it is presented internally, which means that the clock must be operating before a reset can take effect. From a power-on state, RESIN

Contextual Info: M80C186XL AC CHARACTERISTICS MAJOR CYCLE TIMINGS READ CYCLE Tc = —55°C to + 125°C, VCc = 5V ±10% All timings are measured at 1.5V and 100 pF loading on CLKOUT unless otherwise noted. All output test conditions are with C l = 50 pF. For AC tests, input V|_ = 0.45V and Vm = 2.4V except at X1 where V ih = V cc ~ 0.5V.