M68Z512 Search Results

M68Z512W

Contextual Info: M68Z512W 4 Mbit 512 Kbit x 8 LOW VOLTAGE, LOW POWER SRAM WITH OUTPUT ENABLE FEATURES SUMMARY • ULTRA LOW DATA RETENTION CURRENT Figure 1. 32-pin TSOP Package – 400nA (typical) – 10µA (max) ■ OPERATION VOLTAGE: 2.7 TO 3.6V ■ 512 Kbit x 8 SRAM WITH OUTPUT ENABLE

Contextual Info: M68Z512 4 Mbit 512Kb x8 Low Power SRAM with Output Enable PRELIMINARY DATA • ULTRA LOW DATA RETENTION CURRENT – 100nA (typical) – 10µA (max) ■ OPERATION VOLTAGE: 5V ±10% ■ 512 Kbit x8 SRAM with OUTPUT ENABLE ■ EQUAL CYCLE and ACCESS TIMES: 70ns

Contextual Info: M68Z512W 4 Mbit 512Kb x8 Low Voltage Low Power SRAM with Output Enable PRELIMINARY DATA • ULTRA LOW DATA RETENTION CURRENT – 600nA (typical) – 10µA (max) ■ OPERATION VOLTAGE: 2.7 to 3.6V ■ 512 Kbit x8 SRAM with OUTPUT ENABLE ■ EQUAL CYCLE and ACCESS TIMES: 70ns

Contextual Info: M68Z512 4 Mbit 512Kb x8 Low Power SRAM with Output Enable • ULTRA LOW DATA RETENTION CURRENT – 100nA (typical) – 10µA (max) ■ OPERATION VOLTAGE: 5V ±10% ■ 512 Kbit x8 SRAM with OUTPUT ENABLE ■ EQUAL CYCLE and ACCESS TIMES: 70ns ■ ■ LOW VCC DATA RETENTION: 2V

M68Z512

Contextual Info: M68Z512 4 Mbit 512Kb x8 Low Power SRAM with Output Enable PRELIMINARY DATA • ULTRA LOW DATA RETENTION CURRENT - 100nA (typical) - 10|iA (max) ■ OPERATION VOLTAGE: 5V ±10% ■ 512 Kbit x8 SRAM with OUTPUT ENABLE ■ EQUAL CYCLE and ACCESS TIMES: 70ns

M68Z512

Contextual Info: M68Z512 4 Mbit 512Kb x8 Low Power SRAM with Output Enable • ULTRA LOW DATA RETENTION CURRENT – 100nA (typical) – 10µA (max) ■ OPERATION VOLTAGE: 5V ±10% ■ 512 Kbit x8 SRAM with OUTPUT ENABLE ■ EQUAL CYCLE and ACCESS TIMES: 70ns ■ LOW VCC DATA RETENTION: 2V

Contextual Info: M68Z512 4 Mbit 512Kb x8 Low Power SRAM with Output Enable • ULTRA LOW DATA RETENTION CURRENT – 100nA (typical) – 10µA (max) ■ OPERATION VOLTAGE: 5V ±10% ■ 512 Kbit x8 SRAM with OUTPUT ENABLE ■ EQUAL CYCLE and ACCESS TIMES: 70ns ■ ■ LOW VCC DATA RETENTION: 2V

Contextual Info: M68Z512W 4 Mbit 512Kb x8 Low Voltage Low Power SRAM with Output Enable PRELIMINARY DATA • ULTRA LOW DATA RETENTION CURRENT – 600nA (typical) – 10µA (max) ■ OPERATION VOLTAGE: 2.7 to 3.6V ■ 512 Kbit x8 SRAM with OUTPUT ENABLE ■ EQUAL CYCLE and ACCESS TIMES: 70ns

Contextual Info: M68Z512W 4Mbit 512Kbit x 8 LOW VOLTAGE, LOW POWER SRAM WITH OUTPUT ENABLE FEATURES SUMMARY • ULTRA LOW DATA RETENTION CURRENT Figure 1. Package – 400nA (typical) – 10µA (max) ■ OPERATION VOLTAGE: 2.7 to 3.6V ■ 512 Kbit x 8 SRAM WITH OUTPUT ENABLE

M68Z512W

Contextual Info: M68Z512W 4 Mbit 512Kb x8 Low Voltage Low Power SRAM with Output Enable PRELIMINARY DATA • ULTRA LOW DATA RETENTION CURRENT – 600nA (typical) – 10µA (max) ■ OPERATION VOLTAGE: 2.7 to 3.6V ■ 512 Kbit x8 SRAM with OUTPUT ENABLE ■ EQUAL CYCLE and ACCESS TIMES: 70ns

M68Z512

Contextual Info: M68Z512 4 Mbit 512 Kbit x 8 Low Power SRAM with Output Enable FEATURES SUMMARY • ULTRA LOW DATA RETENTION CURRENT Figure 1. Package – 100nA (typical) – 10µA (max) ■ OPERATION VOLTAGE: 5.0V ± 10% ■ 512 Kbit x 8 SRAM WITH OUTPUT ENABLE ■ EQUAL CYCLE and ACCESS TIMES: 70ns

Contextual Info: M68Z512 4 Mbit 512Kb x8 Low Power SRAM with Output Enable • ULTRA LOW DATA RETENTION CURRENT – 100nA (typical) – 10µA (max) ■ OPERATION VOLTAGE: 5V ±10% ■ 512 Kbit x8 SRAM with OUTPUT ENABLE ■ EQUAL CYCLE and ACCESS TIMES: 70ns ■ ■ LOW VCC DATA RETENTION: 2V

M68Z512

Contextual Info: M68Z512 4 Mbit 512Kb x8 Low Power SRAM with Output Enable • ULTRA LOW DATA RETENTION CURRENT – 100nA (typical) – 10µA (max) ■ OPERATION VOLTAGE: 5V ±10% ■ 512 Kbit x8 SRAM with OUTPUT ENABLE ■ EQUAL CYCLE and ACCESS TIMES: 70ns ■ ■ LOW VCC DATA RETENTION: 2V

M68Z128Y

Abstract: Lithium Battery
Contextual Info: M41ST85Y M41ST85W 512 bit 64b x 8 Serial Access RTC and NVRAM SUPERVISOR PRELIMINARY DATA • 3V OR 5V OPERATING VOLTAGE ■ SERIAL INTERFACE SUPPORTS I2C BUS (400 KHz) ■ NVRAMSUPERVISORfor EXTERNAL LPSRAM ■ OPTIMIZED for MINIMAL INTERCONNECT to MCU

ABE smd

Contextual Info: M41ST85Y M41ST85W 5V or 3V, 512 Kbit 64 bit x 8 SERIAL ACCESS RTC and NVRAM SUPERVISOR PRELIMINARY DATA FEATURES SUMMARY • 5V OR 3V OPERATING VOLTAGE SUPPORTS I2C Figure 1. 28-pin SOIC Package ■ SERIAL INTERFACE (400 KHz) ■ NVRAM SUPERVISOR FOR EXTERNAL

TSOP32 FOOTPRINT

Abstract: NVRAM 1KB SOH28 PCB FOOTPRINT M41T81 m48t35 M48T86 M48Z128 M48Z128V M48Z128Y M48Z129V
Contextual Info: Non-Volatile RAMs KEEP TIME, PROTECT DATA NVRAM products offer fast non-volatile memory solutions up to 16 Mbit density using battery backed SRAM, in both surface mount and through-hole packages. Integrated features include battery and crystal, real time clock, watchdog timer, power-on reset, square wave

M41Txx

Abstract: SO16 M48Z35A M48T35A m48t35 M48Z128 M48Z129 M48Z2M1 M48Z35 M48Z512A
Contextual Info: Non-Volatile -Volatile RAM Non RAM Selection Tables Selection Tables STMicroelectronics NVRAM Selection Tables July 2000 ZEROPOWER M48Zxxx TIMEKEEPER M48Txxx M48STxxx NVRAM SUPERVISOR M40Zxxx M40SZxxx M48Txxx Optional Low Power SRAM M68Zxxx SERIAL RTC

M41ST85W

Abstract: M41ST85Y M4TXX-BR12SH SOH28 AN1012 M68Z128Y serial alarm rtc
Contextual Info: M41ST85Y M41ST85W 5.0 OR 3.0V, 512 bit 64 x 8 SERIAL RTC and NVRAM SUPERVISOR FEATURES SUMMARY • 5.0 OR 3.0V OPERATING VOLTAGE SUPPORTS I2C Figure 1. 28-pin SOIC Package ■ SERIAL INTERFACE (400 KHz) ■ NVRAM SUPERVISOR FOR EXTERNAL LPSRAM ■ OPTIMIZED FOR MINIMAL INTERCONNECT

Contextual Info: M41ST85Y M41ST85W 5.0 OR 3.0V, 512 bit 64 x 8 SERIAL RTC and NVRAM SUPERVISOR FEATURES SUMMARY • 5.0 OR 3.0V OPERATING VOLTAGE SUPPORTS I2C Figure 1. 28-pin SOIC Package ■ SERIAL INTERFACE (400 KHz) ■ NVRAM SUPERVISOR FOR EXTERNAL LPSRAM ■ OPTIMIZED FOR MINIMAL INTERCONNECT

Contextual Info: M41ST85Y M41ST85W 5.0 OR 3.0V, 512 bit 64 x 8 SERIAL RTC and NVRAM SUPERVISOR FEATURES SUMMARY • 5.0 OR 3.0V OPERATING VOLTAGE ■ SERIAL INTERFACE SUPPORTS (400 KHz) I2C NVRAM SUPERVISOR FOR EXTERNAL LPSRAM ■ OPTIMIZED FOR MINIMAL INTERCONNECT TO MCU

M41ST85W

Abstract: M41ST85Y M4TXX-BR12SH SOH28 ABE 027
Contextual Info: M41ST85Y M41ST85W 5.0 OR 3.0V, 512 bit 64 x 8 SERIAL RTC and NVRAM SUPERVISOR FEATURES SUMMARY • 5.0 OR 3.0V OPERATING VOLTAGE I2C Figure 1. 28-pin SOIC Package ■ SERIAL INTERFACE SUPPORTS (400 KHz) ■ NVRAM SUPERVISOR FOR EXTERNAL LPSRAM ■ OPTIMIZED FOR MINIMAL INTERCONNECT

a7 surface mount diode

Abstract: SOH28 M48Z512A M48Z512AV M48Z512AY
Contextual Info: M48Z512A M48Z512AY, M48Z512AV* 4 Mbit 512 Kbit x 8 ZEROPOWER SRAM FEATURES SUMMARY • INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, and BATTERY ■ CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES ■ 10 YEARS OF DATA RETENTION IN THE

M40Z300W

Abstract: M41T315V M48T254V M68Z512W A1827
Contextual Info: M48T254V 3.3V, 16 Mbit 2Mb x 8bit TIMEKEEPER SRAM with Phantom Clock NOT FOR NEW DESIGN FEATURES SUMMARY • ■ ■ ■ ■ ■ ■ ■ ■ ■ 3.3V ± 10% INTEGRATED ULTRA LOW POWER SRAM, REAL TIME CLOCK, POWER-FAIL CONTROL CIRCUIT, BATTERY AND CRYSTAL

A1EA

Abstract: M41ST85W M41ST85Y M4TXX-BR12SH SOH28
Contextual Info: M41ST85Y M41ST85W 512 Kbit 64 bit x 8 Serial Access RTC and NVRAM SUPERVISOR PRELIMINARY DATA FEATURES SUMMARY • 3V or 5V OPERATING VOLTAGE SUPPORTS I2C Figure 1. Packages ■ SERIAL INTERFACE (400 KHz) ■ NVRAM SUPERVISOR for EXTERNAL LPSRAM ■ OPTIMIZED for MINIMAL INTERCONNECT to