M6625 Search Results

0D96

Abstract: 28P2W-C M66255FP photocopiers Nk d9
Contextual Info: MITSUBISHI MITSUBISHI 〈DIGITAL 〈DIGITAL ASSP〉 ASSP〉 M66255FP M66255FP 8192 x 10-BIT LINE MEMORY FIFO 8192 × 10-BIT LINE MEMORY (FIFO) DESCRIPTION The M66255FP is a high-speed line memory with a FIFO (First In First Out) structure of 8192-word × 10-bit configuration which uses high-performance silicon gate CMOS process technology.

Contextual Info: MITSUBISHI DIGITAL ASSP M66257FP 51 20 x 8-B IT x 2 LINE M E M O R Y (F IFO ) DESCRIPTION PIN CONFIGURATION (TOP VIEW) T h e M 6 6 2 5 7 F P is a h ig h -s p e e d line m e m o ry w ith a F IF O (First In First O u t) structure of 5 1 2 0 -w o rd x 8-b it do uble c on­

Contextual Info: MITSUBISHI <DIGITAL ASSP> M66258FP 8192 x 8-BIT LINE MEMORY DESCRIPTION The M 66258FP is h ig h speed lin e m e m o ry th a t u s e s high PIN CONFIGURATION TOP VIEW p e rfo rm a n c e s ilic o n g a te C M O S p ro c e s s te c h n o lo g y a n d a d o p ts

M66253FP

Contextual Info: bSH^öES 0024b30 433 BSHIT1 5K BYTE X 2 FIFO MEMORY I SEMICONDUCTOR TWO BUILT-IN 5K BYTE FIFO MEMORY CIRCUITS HIGH-SPEED FIFO MEMORY SUITABLE FOR DIGITAL PLAIN-M PER COPIERS Ne w s M66253FP The M 66253FP is designed to operate at higher speeds than the conventional

Contextual Info: MITSUBISHI DIGITAL ASSP M66251L 5120 x 8-BIT LINE MEMORY (FIFO) DESCRIPTION The M66251L is a high-speed line memory with a FIFO (First In First Out) structure of 5120-word x 8-bit configuration which uses high-performance silicon gate CMOS process technology.

m66253

Contextual Info: MITSUBISHI SEMICONDUCTORS DIG./ANA. ICs M66253FP HIGH SPEED LINE MEMORY WITH FIFO DESCRIPTION Using the high performance silicon-gate CMOS technology, the M66253 is a high speed line memory with a FIFO (First In First Out) structure in a 5120 x 8bit x 2 organization.

Contextual Info: M66256FP IL08D C-MOS 40 M 5,120 x 8 -BIT LINE MEMORY —TOP VIEW— 13 24 D0 IN Q0 OUT 1 Q1 OUT 2 23 D1 IN Q2 OUT 3 22 D2 IN Q3 OUT 4 21 D3 IN 14 15 16 21 22 23 RE IN 5 20 WE IN RRES IN 6 19 WRES IN 7 GND VDD 18 17 WCK IN Q4 OUT 9 16 D4 IN Q5 OUT 10 15 D5 IN

Contextual Info: MITSUBISHI DIGITAL ASSP M66255FP 8192 x 10-BIT LINE MEMORY (FIFO) DESCRIPTION The M66255FP is a high-speed line m em ory with a FIFO (First In First Out) structure of 8192-word x 10-bit configura­ tion which uses high-perform ance silicon gate CMOS pro­

Contextual Info: MITSUBISHI {DIGITAL ASSP M66257FP 5120 x 8-BIT x 2 LINE MEMORY FIFO) PIN CONFIGURATION (TOP VIEW) Eo K Œ Q 02Í— E Q03«— E O 04<- E O 05<- Œ O06 <- E s O 07<- Œ m Q11 «- E "0 m n Digital photocopiers, high-speed facsimile, laser beam print­ ers.

M66259FP

Contextual Info: MITSUBISHI <DIGITAL ASSP> M66259FP 8192 x 8-BIT x 2 LINE MEMORY DESCRIPTION PIN CONFIGURATION TOP VIEW The M66259 is high speed line memory that uses high performance silicon gate CMOS process technology and adopts the FIFO (First In First Out) structure consisting of 8192 words x 8 bits x 2.

66256FP

Abstract: fifo "digital delay line"
Contextual Info: MITSUBISHI DIGITAL ASSP M66256FP 5120 x 8-BIT LINE MEMORY (FIFO) DESCRIPTION PIN CONFIGURATION (TOP VIEW) The M 66256FP is a high-speed line m em ory with a FIFO (First In First Out) structure of 5120-word x 8-bit configuration which uses high-perform ance silicon gate CMOS process

Contextual Info: MITSUBISHI DIGITAL ASSP M66252P/FP 1152 x 8-BIT LINE MEMORY (FIFO) DESCRIPTION The M66252P/FP is a high-speed line memory with a FIFO (First In First Out) structure of 1152-word x 8-bit configuration which uses high-performance silicon gate CMOS process

Contextual Info: MITSUBISHI DIGITAL ASSP> M66255FP 8192 x 10-BIT LINE MEMORY (FIFO DESCRIPTION T h e M 66 25 5F P is a h ig h -s p e e d line m e m o ry w ith a F IF O (First In First O ut) structure of 81 9 2 -w o rd x 10-bit co n fig u ra ­ tion w h ich uses h ig h -p e rfo rm a n c e silico n gate C M O S p ro ­

Contextual Info: MITSUBISHI DIGITAL ASSP M66256FP 5120 x 8-BIT LINE MEMORY (FIFO) DESCRIPTION The M66256FP is a high-speed line m em ory with a FIFO (First In First Out) structure of 5120-word x 8-bit configuration which uses high-perform ance silicon gate CM OS process

M66256

Abstract: M66256FP
Contextual Info: MITSUBISHI MITSUBISHI 〈DIGITAL 〈DIGITAL ASSP〉 ASSP〉 M66256FP M66256FP 5120 x 8-BIT LINE MEMORY FIFO 5120 × 8-BIT LINE MEMORY (FIFO) DESCRIPTION The M66256FP is a high-speed line memory with a FIFO (First In First Out) structure of 5120-word × 8-bit configuration

M66256

Abstract: M66256FP
Contextual Info: M66256FP 5120 x 8-Bit Line Memory FIFO REJ03F0250-0200 Rev.2.00 Sep 14, 2007 Description The M66256FP is a high-speed line memory with a FIFO (First In First Out) structure of 5120-word × 8-bit configuration which uses high-performance silicon gate CMOS process technology.

M66258

Abstract: M66258FP
Contextual Info: M66258FP 8192 x 8-Bit Line Memory REJ03F0252-0200 Rev.2.00 Sep 14, 2007 Description The M66258FP is high speed line memory that uses high performance silicon gate CMOS process technology and adopts the FIFO First In First Out structure consisting of 8192 words × 8 bits.

m66258fp

Abstract: M66258
Contextual Info: MITSUBISHI <DIGITAL ASSP> M66258FP 8192 x 8-BIT LINE MEMORY DESCRIPTION The M66258FP is high speed line memory that uses high performance silicon gate CMOS process technology and adopts the FIFO First In First Out structure consisting of 8192 words x 8 bits.

1152

Abstract: 1152-word
Contextual Info: MITSUBISHI MITSUBISHI 〈DIGITAL 〈DIGITAL ASSP〉 ASSP〉 M66252P/FP M66252P/FP 1152 x 8-BIT LINE MEMORY FIFO 1152 x 8-BIT LINE MEMORY (FIFO) FEATURES • Memory construction . . 1152words x 8bits (dynamic memory)

Contextual Info: MITSUBISHI DIGITAL ASSP M66255FP 8192 x 10-BIT LINE MEMORY (FIFO) DESCRIPTION The M66255FP is a high-speed line memory with a FIFO (First In First Out) structure of 8192-word x 10-bit configura­ tion which uses high-performance silicon gate CMOS pro­ cess technology.

Contextual Info: M IT S U B IS H I < DIGITAL A SS P> M66250P/FP 5 1 2 0 X 8 -B IT L IN E M E M O R Y F IF O /L IF O DESCRIPTION T h e M 6 6 2 5 0 P /F P is an in teg ra te d circuit consisting of a h ig h -s p e e d line m em ory with a F IF O PIN CONFIGURATION (TOP VIEW)

m66251

Abstract: m66251p 24P2W
Contextual Info: S b2M1ä5S 0DS4b57 W MMIT1 5K BYTE FIFO MEMORY SEMICONDUCTOR FIFO FUNCTION, l-LINE MEMORY CAPACITY ARE BUILT-IN HIGH-SPEED LINE MEMORY SUITABLE FOR DIGITAL PPC News M66251P/FP/L A P P L I C A T I High-speed picture data processing. «FIFO Function Built-in First-In First-Out Function for

Contextual Info: MITSUBISHI DIGITAL ASSP M66252P/FP 1152 x 8 -BIT LIN E M E M O R Y (FIFO ) DESCRIPTION PIN CONFIGURATION (TOP VIEW) T h e M 66 25 2P /F P is a h igh -spee d line m em o ry w ith a F IFO (First In First O ut) structure of 1152-word x 8-bit configuration w h ich uses h ig h -p e rfo rm a n c e silico n gate C M O S p ro c e s s

M66257

Abstract: M66257FP
Contextual Info: MITSUBISHI MITSUBISHI 〈DIGITAL 〈DIGITAL ASSP〉 ASSP〉 M66257FP M66257FP 5120 x 8-BIT 2 LINE MEMORY FIFO 5120 × 8-BIT × 2×LINE MEMORY (FIFO) DESCRIPTION The M66257FP is a high-speed line memory with a FIFO (First In First Out) structure of 5120-word × 8-bit double configuration which uses high-performance silicon gate CMOS