M13S128324A Search Results

M13S128324A Datasheets (4)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
M13S128324A		Elite Semiconductor Memory Technology	1M x 32 Bit x 4 Banks Double Data Rate SDRAM		Original	PDF
M13S128324A		Unknown	Modify typing error of Pin Arrangement		Original	PDF
M13S128324A-5BG		Unknown	Modify typing error of Pin Arrangement		Original	PDF
M13S128324A-6BG		Unknown	Modify typing error of Pin Arrangement		Original	PDF

M13S128324A Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
M13S128324A-5BG Abstract: M13S128324A Contextual Info: ESMT M13S128324A DDR SDRAM 1M x 32 Bit x 4 Banks Double Data Rate SDRAM Features z JEDEC Standard z Internal pipelined double-data-rate architecture, two data access per clock cycle z Bi-directional data strobe DQS z On-chip DLL z Differential clock inputs (CLK and CLK )	Original	M13S128324A M13S128324A-5BG M13S128324A	PDF
Contextual Info: ESM T M13S128324A 2M DDR SDRAM 1M x 32 Bit x 4 Banks Double Data Rate SDRAM Features Double-data-rate architecture, two data transfers per clock cycle Bi-directional data strobe (DQS) Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition	Original	M13S128324A	PDF
M13S128324A Contextual Info: ESMT M13S128324A Operation Temperature Condition -40~85°C Revision History Revision 1.0 Dec. 14 2007 -Original Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2007 Revision : 1.0 1/49 ESMT M13S128324A Operation Temperature Condition -40~85°C	Original	M13S128324A M13S128324A	PDF
Contextual Info: ESM T M13S128324A 2M Operation Temperature Condition -40°C~85°C DDR SDRAM 1M x 32 Bit x 4 Banks Double Data Rate SDRAM Features Double-data-rate architecture, two data transfers per clock cycle Bi-directional data strobe (DQS) Differential clock inputs (CLK and CLK )	Original	M13S128324A	PDF
K 872 Abstract: M13S128324A Contextual Info: ESMT M13S128324A Revision History Revision 0.1 May. 13 2005 -Original Revision 0.2 (Aug. 08 2005) -Delete Non-Pb-free of ordering information -Modify typing error of Pin Arrangement Revision 1.0 (Mar. 08 2006) -Delete “Preliminary” at every page -Modify tWR from 2clk to 15ns	Original	M13S128324A K 872 M13S128324A	PDF
DDR SDRAM Contextual Info: ESMT M13S128324A 2M Operation Temperature Condition -40°C~85°C DDR SDRAM 1M x 32 Bit x 4 Banks Double Data Rate SDRAM Features z Double-data-rate architecture, two data transfers per clock cycle z Bi-directional data strobe (DQS) z Differential clock inputs (CLK and CLK )	Original	M13S128324A DDR SDRAM	PDF
M13S128324A Contextual Info: ESMT M13S128324A Revision History Revision 0.1 May. 13 2005 -Original Revision 0.2 (Aug. 08 2005) -Delete Non-Pb-free of ordering information -Modify typing error of Pin Arrangement Revision 1.0 (Mar. 08 2006) -Delete “Preliminary” at every page -Modify tWR from 2clk to 15ns	Original	M13S128324A M13S128324A	PDF
M13S128324A Contextual Info: ESMT M13S128324A Revision History Revision 0.1 May. 13 2005 -Original Revision 0.2 (Aug. 08 2005) -Delete Non-Pb-free of ordering information -Modify typing error of Pin Arrangement Revision 1.0 (Mar. 08 2006) -Delete “Preliminary” at every page -Modify tWR from 2clk to 15ns	Original	M13S128324A M13S128324A	PDF
Contextual Info: ESMT M13S128324A Revision History Revision 0.1 May. 13 2005 -Original Revision 0.2 (Aug. 08 2005) -Delete Non-Pb-free of ordering information -Modify typing error of Pin Arrangement Revision 1.0 (Mar. 08 2006) -Delete “Preliminary” at every page -Modify tWR from 2clk to 15ns	Original		PDF
DDR SDRAM Contextual Info: ESMT M13S128324A 2M DDR SDRAM 1M x 32 Bit x 4 Banks Double Data Rate SDRAM Features z Double-data-rate architecture, two data transfers per clock cycle z Bi-directional data strobe (DQS) z Differential clock inputs (CLK and CLK ) z DLL aligns DQ and DQS transition with CLK transition	Original	M13S128324A DDR SDRAM	PDF
M13S128324A Contextual Info: ESMT M13S128324A Revision History Revision 0.1 May. 13 2005 -Original Revision 0.2 (Aug. 08 2005) -Delete Non-Pb-free of ordering information -Modify typing error of Pin Arrangement Revision 1.0 (Mar. 08 2006) -Delete “Preliminary” at every page -Modify tWR from 2clk to 15ns	Original	M13S128324A M13S128324A	PDF
Contextual Info: ESMT Preliminary M13S128324A Revision History Revision 0.1 May. 13 2005 -Original Revision 0.2 (Aug. 08 2005) -Delete Non-Pb-free of ordering information -Modify typing error of Pin Arrangement Elite Semiconductor Memory Technology Inc. Publication Date : Aug. 2005	Original	M13S128324A	PDF
Contextual Info: ESMT M13S128324A Revision History Revision 0.1 May. 13 2005 -Original Revision 0.2 (Aug. 08 2005) -Delete Non-Pb-free of ordering information -Modify typing error of Pin Arrangement Revision 1.0 (Mar. 08 2006) -Delete “Preliminary” at every page -Modify tWR from 2clk to 15ns	Original	M13S128324A	PDF
Contextual Info: ESMT M13S128324A Revision History Revision 0.1 May. 13 2005 -Original Revision 0.2 (Aug. 08 2005) -Delete Non-Pb-free of ordering information -Modify typing error of Pin Arrangement Revision 1.0 (Mar. 08 2006) -Delete “Preliminary” at every page -Modify tWR from 2clk to 15ns	Original	M13S128324A	PDF