LVTTL Search Results

Contextual Info: SN54GTL1655, SN74GTL1655 16-BIT LVTTL TO GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS WITH LIVE INSERTION SCBS696C - JULY 1997 - REVISED MAY 1998 Members of the Texas Instruments Widebus Family SN74G TL1655 . . . DGG PACKAGE TOP VIEW Translate Between GTL/GTL+ Signal Level

Contextual Info: CDC351 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS SC AS339-FEBRU ARY 1994-R E V IS E D MARCH 1994 DB OR DW PACKAGE TOP VIEW Low Output Skew, Low Pulse Skew for Clock-Distributlon and Clock-Generation Applications Operates at 3.3 Vcc LVTTL-Compatlble Inputs and Outputs

SMOS182

Contextual Info: TMS626802, TMS636802 1048576-WORD BY 8-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES SMOS182 - FEBRUARY 1994 TM S626802 LVTTL DGE PACKAGE (TO P VIE W ) 3.3-V Power Supply (10% Tolerance) Two Banks for On-Chip Interleaving (Gapless Accesses) vcc [ 1

Contextual Info: SN74HSTL16918 9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES096C – APRIL 1997 – REVISED JANUARY 1999 D D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Inputs Meet JEDEC HSTL Std JESD 8-6 and Outputs Meet Level III Specifications

NB6N11SMNG

Contextual Info: NB6N11S 3.3 V 1:2 AnyLevelE Input to LVDS Fanout Buffer / Translator Description The NB6N11S is a differential 1:2 Clock or Data Receiver and will accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These signals will be translated to LVDS and two identical

Contextual Info: SN74GTLPH1645 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER www.ti.com FEATURES • • • • • • • • • • • • Member of the Texas Instruments Widebus Family TI-OPC™ Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC™ Circuitry Improves Signal Integrity and

Contextual Info: SN74GTLPH1616 17-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS www.ti.com FEATURES • • • • • • • • • • • • • • • Member of the Texas Instruments Widebus Family UBT™ Transceiver Combines D-Type Latches

Contextual Info: SN74VMEH22501AĆEP 8ĆBIT UNIVERSAL BUS TRANSCEIVER AND TWO 1ĆBIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3ĆSTATE OUTPUTS SCES625 − FEBRUARY 2005 D Controlled Baseline D D D D D D D D D D D D D D D D D D DGG OR DGV PACKAGE TOP VIEW

Contextual Info: 3V LVTTL-TO-DIFFERENTIAL LVPECL AND DIFFERENTIAL LVPECL-TO-LVTTL TRANSLATOR SY10EPT28L SY100EPT28L FINAL FEATURES • 3.3V ±10% power supply ■ Guaranteed AC parameters over temperature: fMAX > 275MHz LVTTL ■ < 2ns LVPECL-to-LVTTL propagation delay ■ < 600ps LVTTL-to-LVPECL propagation delay

K4S511632D

Contextual Info: K4S511632D CMOS SDRAM DDP 512Mbit SDRAM 8M x 16bit x 4 Banks Synchronous DRAM LVTTL Revision 0.0 July. 2002 This is to advise Samsung customers that in accordance with certain terms of an agreement, Samsung is prohibited from selling any DRAM products configured in "Multi-Die Plastic" format for use as components in general and scientific computers, such as mainframes, servers,

A67L7332

Abstract: A67L7336 A67L8316 A67L8318
Contextual Info: A67L8316/A67L8318/ A67L7332/A67L7336 Series 256K X 16/18, 128K X 32/36 Preliminary LVTTL, Pipelined DBA SRAM Document Title 256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM Revision History Rev. No. 0.0 PRELIMINARY History Issue Date Remark Initial issue

SY100EPT22V

Abstract: SY89322V SY89322VMGTR SY89322VMITR footprint mlf amkor exposed pad M9999-060809
Contextual Info: 3.3V/5V DUAL LVTTL/LVCMOS-to-DIFFERENTIAL LVPECL TRANSLATOR Micrel, Inc. SY89322V Precision Edge SY89322V FEATURES • ■ ■ ■ ■ ■ ■ ■ 3.3V and 5V power supply option 300ps typical propagation delay Differential LVPECL outputs PNP LVTTL inputs for minimal loading

K4S280832D

Contextual Info: K4S280832D CMOS SDRAM 128Mbit SDRAM 4M x 8Bit x 4 Banks Synchronous DRAM LVTTL Rev. 0.1 Sept. 2001 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.1 Sept. 2001 K4S280832D CMOS SDRAM Revision History Revision 0.0 July, 2001

K4S280432C

Abstract: K4S280432D
Contextual Info: K4S280432D CMOS SDRAM 128Mbit SDRAM 8M x 4Bit x 4 Banks Synchronous DRAM LVTTL Rev. 0.1 Sept. 2001 * Samsung Electronics reserves the right to change products or specification without notice. Rev.0.1 Sept. 2001 K4S280432D CMOS SDRAM Revision History Revision 0.0 Mar., 2001

K4S561632C-TC/L75

Abstract: K4S561632C K4S561632C-TC K4S561632C-TC/L7C
Contextual Info: K4S561632C CMOS SDRAM 256Mbit SDRAM 4M x 16bit x 4 Banks Synchronous DRAM LVTTL Revision 0.4 Sept. 2001 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.4 Sept. 2001 K4S561632C CMOS SDRAM Revision History

A115-A

Abstract: C101 SN74GTLP817 SN74GTLP817DW SN74GTLP817DWR
Contextual Info: SN74GTLP817 GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER SCES285C – OCTOBER 1999 – REVISED FEBRUARY 2001 D D D D D D D D D D D D DGV, DW, OR PW PACKAGE TOP VIEW OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP

GTL2018PW

Abstract: JESD22-A114 JESD22-A115 JESD78 TSSOP24
Contextual Info: GTL2018 8-bit LVTTL to GTL transceiver Rev. 01 — 15 February 2007 Product data sheet 1. General description The GTL2018 is an octal translating transceiver designed for 3.3 V LVTTL system interface with a GTL−/GTL/GTL+ bus. The direction pin DIR allows the part to function as either a GTL-to-LVTTL sampling

Contextual Info: SN74GTLPH32916 34-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS www.ti.com SCES380A – JANUARY 2002 – REVISED JUNE 2005 FEATURES • • • • • • • • Member of the Texas Instruments Widebus+ Family UBT™ Transceiver Combines D-Type Latches

Contextual Info: www.ti.com SN74GTL16622A 18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER SCBS673F – AUGUST 1996 – REVISED APRIL 2005 FEATURES • • • • • • • • • • Member of Texas Instruments Widebus Family OEC™ Circuitry Improves Signal Integrity and

Contextual Info: SK100ELT23W Dual Differential PECL to CMOS/TTL Translator PRELIMINARY HIGH-PERFORMANCE PRODUCTS Description Features The SK100ELT23W is a dual differential PECL to CMOS/TTL or LVCMOS/LVTTL Translator. Since PECL Positive ECL levels are used, only positive VCC and

Contextual Info: SN74GTLPH32912 36-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER www.ti.com FEATURES • • • • • • • Member of the Texas Instruments Widebus+ Family UBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, and

27BSC

Abstract: AS1154 AS1156
Contextual Info: D a ta S he e t A S 11 5 6 / A S 11 5 4 S i n g l e / D u a l LV D S D r i v e r 1 General Description 2 Key Features The AS1156/AS1154 is a Single/Dual Flow-Through LVDS Low-Voltage Differential Signaling Line Driver which accepts and converts LVTTL/LVCMOS input levels into LVDS output signals. The device is perfect for

KPT25

Abstract: EPT25 MC100EPT25 MC100EPT25D MC100EPT25DR2 MC100EPT25DT MC100EPT25DTR2 KA25 kpt25 alyw
Contextual Info: MC100EPT25 −3.3V / −5V Differential ECL to +3.3V LVTTL Translator The MC100EPT25 is a Differential ECL to LVTTL translator. This device requires +3.3 V, -3.3 V to -5.2 V, and ground. The small outline 8-lead package and the single gate of the EPT25 make it ideal

15-V

Abstract: SN74HSTL16918
Contextual Info: SN74HSTL16918 9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES096C – APRIL 1997 – REVISED JANUARY 1999 D D D D D DGG PACKAGE TOP VIEW Member of the Texas Instruments Widebus Family Inputs Meet JEDEC HSTL Std JESD 8-6 and Outputs Meet Level III Specifications