LVC74A Search Results

Contextual Info: LVC74A-Q1 www.ti.com . SCES481C – AUGUST 2003 – REVISED APRIL 2008 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

LC74A

Contextual Info: LVC74A, LVC74A www.ti.com SCAS287T – JANUARY 1993 – REVISED JULY 2013 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET Check for Samples: LVC74A, LVC74A FEATURES DESCRIPTION • • • • The LVC74A dual positive-edge-triggered Dtype flip-flop is designed for 2.7-V to 3.6-V VCC

Contextual Info: 3.3V CMOS DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET, 5 VOLT TOLERANT I/O FEATURES: - 0.5 MICRON CMOS Technology - ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 - 1,27mm pitch SOIC, 0.635mm pitch QSOP,

IDT74LVC74A

Abstract: LVC74A
Contextual Info: LVC74A 3.3V CMOS POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET, 5 VOLT TOLERANT I/O DESCRIPTION FEATURES: – – – – – – – – –

lc74a

Abstract: A115-A C101 SN54LVC74A SN74LVC74A lvc74a
Contextual Info: LVC74A, LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS287P – JANUARY 1993 – REVISED SEPTEMBER 2002 3 12 4 11 5 10 6 9 7 8 1D 1CLK 1PRE 1Q 1Q 14 13 2CLR 3 12 2D 4 11 2CLK 5 10 2PRE 9 2Q 6 7 8 1CLK NC 1PRE NC 1Q

LVC74A

Contextual Info: LVC74A 3.3V CMOS DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET, 5 VOLT TOLERANT I/O LVC74A DESCRIPTION: FEATURES: This dual positive-edge-triggered D-type flip-flop is built using advanced

Contextual Info: LVC74A, LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET www.ti.com SCAS287S – JANUARY 1993 – REVISED MAY 2005 • 3 12 4 11 5 10 6 9 7 8 1D 1CLK 1PRE 1Q 1Q 1 14 1D VCC 2CLR 2D 2CLK 2PRE 2Q 2Q LVC74A . . . FK PACKAGE

Contextual Info: LVC74A, LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET www.ti.com SCAS287S – JANUARY 1993 – REVISED MAY 2005 • 3 12 4 11 5 10 6 9 7 8 1D 1CLK 1PRE 1Q 1Q 1 14 1D VCC 2CLR 2D 2CLK 2PRE 2Q 2Q LVC74A . . . FK PACKAGE

Contextual Info: LVC74A-EP DUAL POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET w w w .t i.c om SCAS751C – DECEMBER 2003 – REVISED SEPTEMBER 2007 FEATURES 1 • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site

Contextual Info: LVC74A, LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET www.ti.com SCAS287S – JANUARY 1993 – REVISED MAY 2005 • 3 12 4 11 5 10 6 9 7 8 1D 1CLK 1PRE 1Q 1Q 1 14 1D VCC 2CLR 2D 2CLK 2PRE 2Q 2Q LVC74A . . . FK PACKAGE

Contextual Info: LVC74A-Q1 www.ti.com . SCES481C – AUGUST 2003 – REVISED APRIL 2008 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

Contextual Info: LVC74A, LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET www.ti.com SCAS287S – JANUARY 1993 – REVISED MAY 2005 • 3 12 4 11 5 10 6 9 7 8 1D 1CLK 1PRE 1Q 1Q 1 14 1D VCC 2CLR 2D 2CLK 2PRE 2Q 2Q LVC74A . . . FK PACKAGE

LCV74A

Contextual Info: LVC74A, LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS287M – JANUARY 1993 – REVISED MARCH 2002 D 1CLR 1D 1CLK 1PRE 1Q 1Q GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE 2Q 2Q LVC74A . . . FK PACKAGE

LCV74A

Abstract: LVC74A
Contextual Info: LVC74A, LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS287N – JANUARY 1993 – REVISED JULY 2002 D D LVC74A . . . J OR W PACKAGE LVC74A . . . D, DB, NS, OR PW PACKAGE TOP VIEW 1CLR 1D 1CLK 1PRE 1Q 1Q GND

LVC125

Abstract: lvc14 lvc04 LVC74A lvc138a LVC00 lvc04a LVC14A lvc08 LVC08A
Contextual Info: TEXAS INSTRUMENTS Informational Notification of Datasheet Changes to Selected LVC Devices September 25, 1996 Abstract Texas Instruments is reducing the maximum limit on various timing specifications on a selected group of LVC devices. This reduction is within the current specification and no changes were made to the die

Contextual Info: LVC74A-EP DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS751A – DECEMBER 2003 – REVISED AUGUST 2005 FEATURES • • • • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication

Contextual Info: LVC74A-EP DUAL POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS751C – DECEMBER 2003 – REVISED SEPTEMBER 2007 FEATURES 1 • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –40°C

Contextual Info: LVC74A 3.3V CMOS DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET, 5 VOLT TOLERANT I/O LVC74A FEATURES: DESCRIPTION: • 0.5 MICRON CMOS Technology

Contextual Info: LVC74A-EP DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS751A – DECEMBER 2003 – REVISED AUGUST 2005 FEATURES • • • • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication

LC74A

Abstract: SN74LVC74ADT A115-A C101 SN54LVC74A SN74LVC74A
Contextual Info: LVC74A, LVC74A DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS WITH CLEAR AND PRESET SCAS287S − JANUARY 1993 − REVISED AUGUST 2004 4 11 5 10 6 9 7 8 1D 1CLK 1PRE 1Q 1Q 1 14 2 13 2CLR 3 12 2D 4 11 2CLK 5 10 2PRE 9 2Q 6 7 8 1CLK NC 1PRE NC 1Q

Contextual Info: LVC74A-EP DUAL POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS751C – DECEMBER 2003 – REVISED SEPTEMBER 2007 FEATURES 1 • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –40°C

Contextual Info: LVC74A-EP DUAL POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS751C – DECEMBER 2003 – REVISED SEPTEMBER 2007 FEATURES 1 • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –40°C

Contextual Info: LVC74A, LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS287P – JANUARY 1993 – REVISED SEPTEMBER 2002 3 12 4 11 5 10 6 9 7 8 1D 1CLK 1PRE 1Q 1Q 14 13 2CLR 3 12 2D 4 11 2CLK 5 10 2PRE 9 2Q 6 7 8 1CLK NC 1PRE NC 1Q

Contextual Info: LVC74A-EP DUAL POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS751C – DECEMBER 2003 – REVISED SEPTEMBER 2007 FEATURES 1 • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –40°C