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    LVC74A Search Results

    LVC74A Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    LVC74AU Renesas Electronics Corporation DUAL POS EDGE TRIGGERED F Visit Renesas Electronics Corporation
    74LVC74ADC8 Renesas Electronics Corporation DUAL POS EDGE TRIGGERED F Visit Renesas Electronics Corporation
    74LVC74APY8 Renesas Electronics Corporation DUAL POS EDGE TRIGGERED F Visit Renesas Electronics Corporation
    74LVC74APG Renesas Electronics Corporation DUAL POS EDGE TRIGGERED F Visit Renesas Electronics Corporation
    74LVC74APG8 Renesas Electronics Corporation DUAL POS EDGE TRIGGERED F Visit Renesas Electronics Corporation
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    LVC74A Price and Stock

    Texas Instruments SN74LVC74AQPWRQ1

    IC FF D-TYPE DUAL 1BIT 14TSSOP
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    DigiKey SN74LVC74AQPWRQ1 Cut Tape 7,881 1
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    SN74LVC74AQPWRQ1 Digi-Reel 7,881 1
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    Chip One Stop SN74LVC74AQPWRQ1 Cut Tape 1,990
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    Texas Instruments SN74LVC74APWR

    IC FF D-TYPE DUAL 1BIT 14TSSOP
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    DigiKey SN74LVC74APWR Reel 4,000 2,000
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    Mouser Electronics SN74LVC74APWR 7,143
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    Newark SN74LVC74APWR Cut Tape 55 5
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    ComSIT USA SN74LVC74APWR 2,167
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    Velocity Electronics SN74LVC74APWR 1,365
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    Chip One Stop SN74LVC74APWR Cut Tape 1,183
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    Chip Stock SN74LVC74APWR 6,325
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    Component Electronics, Inc SN74LVC74APWR 3,024
    • 1 $1.15
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    • 100 $0.87
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    Win Source Electronics SN74LVC74APWR 210,400
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    Texas Instruments SN74LVC74ARGYR

    IC FF D-TYPE DUAL 1BIT 14VQFN
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey SN74LVC74ARGYR Reel 3,000 3,000
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    Mouser Electronics SN74LVC74ARGYR 3,077
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    Rochester Electronics SN74LVC74ARGYR 102,159 1
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    Nexperia 74LVC74APW,118

    IC FF D-TYPE DUAL 1BIT 14TSSOP
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    DigiKey 74LVC74APW,118 Reel 2,500 2,500
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    Avnet Americas 74LVC74APW,118 Reel 8 Weeks 10,000
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    Mouser Electronics 74LVC74APW,118 6,115
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    Newark 74LVC74APW,118 Cut Tape 1,175 5
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    Rochester Electronics 74LVC74APW,118 37,900 1
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    TTI 74LVC74APW,118 Reel 25,000 2,500
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    TME 74LVC74APW,118 1
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    Avnet Asia 74LVC74APW,118 15,000 8 Weeks 10,000
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    Avnet Silica 74LVC74APW,118 40,000 10 Weeks 2,500
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    Chip One Stop 74LVC74APW,118 Cut Tape 2,029
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    Chip Stock 74LVC74APW,118 2,113
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    EBV Elektronik 74LVC74APW,118 10 Weeks 2,500
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    New Advantage Corporation 74LVC74APW,118 37,500 1
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    Texas Instruments SN74LVC74AQDRG4Q1

    IC FF D-TYPE DUAL 1BIT 14SOIC
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey SN74LVC74AQDRG4Q1 Cut Tape 2,186 1
    • 1 $0.46
    • 10 $0.325
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    SN74LVC74AQDRG4Q1 Digi-Reel 2,186 1
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    Find more LVC74A price and stock on Findchips.com

    LVC74A Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    Untitled

    Abstract: No abstract text available
    Text: LVC74A-Q1 www.ti.com . SCES481C – AUGUST 2003 – REVISED APRIL 2008 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP


    Original     		SN74LVC74A-Q1 SCES481C MIL-STD-883, PDF

    LC74A

    Abstract: No abstract text available
    Text: LVC74A, LVC74A www.ti.com SCAS287T – JANUARY 1993 – REVISED JULY 2013 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET Check for Samples: LVC74A, LVC74A FEATURES DESCRIPTION • • • • The LVC74A dual positive-edge-triggered Dtype flip-flop is designed for 2.7-V to 3.6-V VCC


    Original     		SN54LVC74A, SN74LVC74A SCAS287T SN54LVC74A SN74LVC74A LC74A PDF

    IDT74LVC74A

    Abstract: LVC74A
    Text: LVC74A 3.3V CMOS POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET, 5 VOLT TOLERANT I/O DESCRIPTION FEATURES: – – – – – – – – –


    Original     		IDT74LVC74A MIL-STD-883, 200pF, 635mm SO14-1) SO14-2) SO14-3) IDT74LVC74A LVC74A PDF

    lc74a

    Abstract: A115-A C101 SN54LVC74A SN74LVC74A lvc74a
    Text: LVC74A, LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS287P – JANUARY 1993 – REVISED SEPTEMBER 2002 3 12 4 11 5 10 6 9 7 8 1D 1CLK 1PRE 1Q 1Q 14 13 2CLR 3 12 2D 4 11 2CLK 5 10 2PRE 9 2Q 6 7 8 1CLK NC 1PRE NC 1Q


    Original     		SN54LVC74A, SN74LVC74A SCAS287P SN54LVC74A SN74LVreproduction lc74a A115-A C101 SN54LVC74A SN74LVC74A lvc74a PDF

    LVC74A

    Abstract: No abstract text available
    Text: LVC74A 3.3V CMOS DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET, 5 VOLT TOLERANT I/O LVC74A DESCRIPTION: FEATURES: This dual positive-edge-triggered D-type flip-flop is built using advanced


    Original     		IDT74LVC74A LVC74A PDF

    Untitled

    Abstract: No abstract text available
    Text: LVC74A, LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET www.ti.com SCAS287S – JANUARY 1993 – REVISED MAY 2005 • 3 12 4 11 5 10 6 9 7 8 1D 1CLK 1PRE 1Q 1Q 1 14 1D VCC 2CLR 2D 2CLK 2PRE 2Q 2Q LVC74A . . . FK PACKAGE


    Original     		SN54LVC74A, SN74LVC74A SCAS287S SN54LVC74A SN74LVC74A 000-V A114-A) A115-A) PDF

    Untitled

    Abstract: No abstract text available
    Text: LVC74A, LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET www.ti.com SCAS287S – JANUARY 1993 – REVISED MAY 2005 • 3 12 4 11 5 10 6 9 7 8 1D 1CLK 1PRE 1Q 1Q 1 14 1D VCC 2CLR 2D 2CLK 2PRE 2Q 2Q LVC74A . . . FK PACKAGE


    Original     		SN54LVC74A, SN74LVC74A SCAS287S SN54LVC74A SN74LVC74A 000-V A114-A) A115-A) PDF

    Untitled

    Abstract: No abstract text available
    Text: LVC74A-EP DUAL POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET w w w .t i.c om SCAS751C – DECEMBER 2003 – REVISED SEPTEMBER 2007 FEATURES 1 • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site


    Original     		SN74LVC74A-EP SCAS751C PDF

    Untitled

    Abstract: No abstract text available
    Text: LVC74A, LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET www.ti.com SCAS287S – JANUARY 1993 – REVISED MAY 2005 • 3 12 4 11 5 10 6 9 7 8 1D 1CLK 1PRE 1Q 1Q 1 14 1D VCC 2CLR 2D 2CLK 2PRE 2Q 2Q LVC74A . . . FK PACKAGE


    Original     		SN54LVC74A, SN74LVC74A SCAS287S SN54LVC74A SN74LVC74A 000-V A114-A) A115-A) PDF

    Untitled

    Abstract: No abstract text available
    Text: LVC74A-Q1 www.ti.com . SCES481C – AUGUST 2003 – REVISED APRIL 2008 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP


    Original     		SN74LVC74A-Q1 SCES481C MIL-STD-883, PDF

    Untitled

    Abstract: No abstract text available
    Text: LVC74A, LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET www.ti.com SCAS287S – JANUARY 1993 – REVISED MAY 2005 • 3 12 4 11 5 10 6 9 7 8 1D 1CLK 1PRE 1Q 1Q 1 14 1D VCC 2CLR 2D 2CLK 2PRE 2Q 2Q LVC74A . . . FK PACKAGE


    Original     		SN54LVC74A, SN74LVC74A SCAS287S SN54LVC74A SN74LVC74A 000-V A114-A) A115-A) PDF

    LCV74A

    Abstract: No abstract text available
    Text: LVC74A, LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS287M – JANUARY 1993 – REVISED MARCH 2002 D 1CLR 1D 1CLK 1PRE 1Q 1Q GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE 2Q 2Q LVC74A . . . FK PACKAGE


    Original     		SN54LVC74A, SN74LVC74A SCAS287M 000-V A114-A) A115-A) SN54LVC74A SN74LVC74A SN54LVC74A LCV74A PDF

    LCV74A

    Abstract: LVC74A
    Text: LVC74A, LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS287N – JANUARY 1993 – REVISED JULY 2002 D D LVC74A . . . J OR W PACKAGE LVC74A . . . D, DB, NS, OR PW PACKAGE TOP VIEW 1CLR 1D 1CLK 1PRE 1Q 1Q GND


    Original     		SN54LVC74A, SN74LVC74A SCAS287N 000-V A114-A) A115-A) SN54LVC74A SN74LVC74A LCV74A LVC74A PDF

    SN74LVC74A

    Abstract: SN74LVC74AMDREP SN74LVC74AMPWREP SN74LVC74AQDREP SN74LVC74AQPWREP
    Text: LVC74A-EP DUAL POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS751C – DECEMBER 2003 – REVISED SEPTEMBER 2007 FEATURES 1 • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –40°C


    Original     		SN74LVC74A-EP SCAS751C SN74LVC74A SN74LVC74AMDREP SN74LVC74AMPWREP SN74LVC74AQDREP SN74LVC74AQPWREP PDF

    Untitled

    Abstract: No abstract text available
    Text: LVC74A-EP DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS751A – DECEMBER 2003 – REVISED AUGUST 2005 FEATURES • • • • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication


    Original     		SN74LVC74A-EP SCAS751A PDF

    Untitled

    Abstract: No abstract text available
    Text: LVC74A-EP DUAL POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS751C – DECEMBER 2003 – REVISED SEPTEMBER 2007 FEATURES 1 • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –40°C


    Original     		SN74LVC74A-EP SCAS751C PDF

    Untitled

    Abstract: No abstract text available
    Text: LVC74A 3.3V CMOS DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET, 5 VOLT TOLERANT I/O LVC74A FEATURES: DESCRIPTION: • 0.5 MICRON CMOS Technology


    Original     		IDT74LVC74A MIL-STD-883, 200pF, IDT74LVC74A PDF

    Untitled

    Abstract: No abstract text available
    Text: LVC74A-EP DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS751A – DECEMBER 2003 – REVISED AUGUST 2005 FEATURES • • • • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication


    Original     		SN74LVC74A-EP SCAS751A PDF

    LC74A

    Abstract: SN74LVC74ADT A115-A C101 SN54LVC74A SN74LVC74A
    Text: LVC74A, LVC74A DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS WITH CLEAR AND PRESET SCAS287S − JANUARY 1993 − REVISED AUGUST 2004 4 11 5 10 6 9 7 8 1D 1CLK 1PRE 1Q 1Q 1 14 2 13 2CLR 3 12 2D 4 11 2CLK 5 10 2PRE 9 2Q 6 7 8 1CLK NC 1PRE NC 1Q


    Original     		SN54LVC74A, SN74LVC74A SCAS287S SN54LVC74A SN74LVC74Aplifiers LC74A SN74LVC74ADT A115-A C101 SN54LVC74A SN74LVC74A PDF

    Untitled

    Abstract: No abstract text available
    Text: LVC74A-EP DUAL POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS751C – DECEMBER 2003 – REVISED SEPTEMBER 2007 FEATURES 1 • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –40°C


    Original     		SN74LVC74A-EP SCAS751C PDF

    Untitled

    Abstract: No abstract text available
    Text: LVC74A-EP DUAL POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS751C – DECEMBER 2003 – REVISED SEPTEMBER 2007 FEATURES 1 • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –40°C


    Original     		SN74LVC74A-EP SCAS751C PDF

    Untitled

    Abstract: No abstract text available
    Text: LVC74A, LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS287P – JANUARY 1993 – REVISED SEPTEMBER 2002 3 12 4 11 5 10 6 9 7 8 1D 1CLK 1PRE 1Q 1Q 14 13 2CLR 3 12 2D 4 11 2CLK 5 10 2PRE 9 2Q 6 7 8 1CLK NC 1PRE NC 1Q


    Original     		SN54LVC74A, SN74LVC74A SCAS287P 000-V A114-A) A115-A) PDF

    Untitled

    Abstract: No abstract text available
    Text: LVC74A-EP DUAL POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS751C – DECEMBER 2003 – REVISED SEPTEMBER 2007 FEATURES 1 • • • • • • 1 Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –40°C


    Original     		SN74LVC74A-EP SCAS751C PDF

    Untitled

    Abstract: No abstract text available
    Text: 3.3V CMOS DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET, 5 VOLT TOLERANT I/O FEATURES: - 0.5 MICRON CMOS Technology - ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 - 1,27mm pitch SOIC, 0.635mm pitch QSOP,


    OCR Scan     		MIL-STD-883, 200pF, 635mm LVC74A: IDT74LVC74A 2975StenderWay PDF