LVC16500A Search Results

LVC16500A Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
Contextual Info: 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O LVC16500A ADVANCE INFORMATION DESCRIPTION: FEATURES: - Typical tsK o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)	OCR Scan	18-BIT IDT74LVC16500A 250ps MIL-STD-883, 200pF, 635mm -400C LVC16500A: 18-bit	PDF
74LVC05 Abstract: 7400 datasheet 2-input nand gate 74LVC05A LVC1G04 transistor x1 pv 25 inverter board design pv 74ALVC1G04 74ALVCH244 7400 nand gate series 74ALVC1G14 Contextual Info: Selector Guide for ALVC/LVC Products the leading provider of high-performance logic. From single-gate to 32-bit, IDT is your source for ALVC/LVC logic. Today’s designers are developing the most challenging telecommunications, networking and PC products ever designed	Original	32-bit, compatibilit-7850 74LVC05 7400 datasheet 2-input nand gate 74LVC05A LVC1G04 transistor x1 pv 25 inverter board design pv 74ALVC1G04 74ALVCH244 7400 nand gate series 74ALVC1G14	PDF
IDT74LVC16500A Abstract: LVC16500A Contextual Info: 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O FEATURES: - Typical - ESD > 2000V per MIL-STD-883, Method 3015; - 0.635mm pitch S SO P , 0.50mm pitch T S S O P tsK o (Output Skew) < 250ps > 200V using machine model (C = 200pF, R = 0)	OCR Scan	18-BIT VC16500A 250ps MIL-STD-883, 200pF, 635mm LVC16500A: S056-1) S056-2) S056-3) IDT74LVC16500A LVC16500A	PDF
S106B1 Abstract: IDT74LVC16500A LVC16500A SO56-2 Contextual Info: LVC16500A 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O LVC16500A DESCRIPTION: FEATURES: – – Typical tSK 0 (Output Skew) < 250ps	Original	IDT74LVC16500A 18-BIT 18-BIT 250ps MIL-STD-883, 200pF, 635mm LVC16500A: SO56-1) S106B1 IDT74LVC16500A LVC16500A SO56-2	PDF
c 4554 Abstract: cmos 4554 IDT74LVC16500A LVC16500A SO56-2 Contextual Info: LVC16500A 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O LVC16500A ADVANCE INFORMATION DESCRIPTION: FEATURES: – – Typical tSK 0 (Output Skew) < 250ps	Original	IDT74LVC16500A 18-BIT 18-BIT 250ps MIL-STD-883, 200pF, 635mm LVC16500A: SO56-1) c 4554 cmos 4554 IDT74LVC16500A LVC16500A SO56-2	PDF
IDT74LVC16500A Abstract: LVC16500A SO56-2 Contextual Info: LVC16500A 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O LVC16500A DESCRIPTION: FEATURES: Typical tSK 0 (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015;	Original	IDT74LVC16500A 18-BIT 18-BIT 250ps MIL-STD-883, 200pF, 635mm LVC16500A: SO56-1) IDT74LVC16500A LVC16500A SO56-2	PDF
6bl7 Contextual Info: 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O LVC16500A ADVANCE INFORMATION DESCRIPTION: FEATURES: - Typical tsK o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)	OCR Scan	18-BIT 250ps MIL-STD-883, 200pF, 635mm LVC16500A: IDT74LVC16500A 6bl7	PDF