LSA200 Search Results

LSA2009

Contextual Info: LSI LOGIC C O R PO R A T IO N LS A 2 0 0 9 Csu T w o M icro n H CM O S Stru ctu red A rr a y 000978 General Description The LSA2009 is a m em ber o f the 2-m icron drawn, 1.4-micron effective HCMOS fa m ily of S tructured A rrays o ffe re d by LSI LOGIC C orporation . These very

Contextual Info: 5 LSI LO G IC C O R P O R A T IO N ' LSA2003 c5 l Tw o M icron HCMOS Structured Array 000976 General Description Arrays provide a high density of logic functionality while maintaining the flexibility of design and fast turn-around of metal mask programmable logicarrays. The use of dual layer metal interconnect

ALU IC 74181 circuit diagram

Abstract: Alu 74181 ALU IC 74181 ALU IC 74181 FUNCTION TABLE ALU 74-181 amd 2900 ALU IC 74181 circuit IC 74181 alu 74181 ic pin diagram 32 bit carry select adder
Contextual Info: LS I lo g ic lì LSA2001 Silicon-Gate HCMOS Structured Array o /'•As t< 2 ! o U 005793 o 1PDescription The LSA2001 is a member of LSI Logic Corporation's 2-micron HCMOS Structured Array family. These very high-performance application-specific integrated cir­

512x64

Abstract: 2901s
Contextual Info: L S I LOGIC CORP Û1 D E | S304Û04 D0D0Û27 b | LSI LO G IC C O R P O R A T IO N General Description The LSA2005 is a member of the 2-micron drawn, 1.4-micron effective HCMOS family of Structured Arrays offered by LSI Logic Corporation. These very high performance, Application Specific Integrated Cir­

GFT1811A

Abstract: 74181 alu 74181 alu 74181 logic Alu 183 32 bit carry select adder
Contextual Info: Table of Contents - Part II The follow ing megafunctions are available in the LL7000 Series, LL9000 Series, and LSA2000 Series of channeled gate array products. M ost of these are also available in the LL5000 Series of gate arrays. M egafunction Name Type

ALU IC 74181 architecture

Abstract: ALU IC 74181 circuit diagram ALU IC 74181 FUNCTION TABLE INTERNAL DIAGRAM OF IC 74181 8 BIT ALU by 74181 circuit ALU 74-181 ALU IC 74181 74181 motorola "alu 4 bit" alu 74181
Contextual Info: LSI M, \ 1 Vy / ' lock LSA2001 SHicon-Gate HCMOS Structured Array , \ f ei 005793 O L S L * Description The LSA2001 is a member of LSI Logic Corporation's 2-micron HCMOS Structured Array family. These very high-performance application-specific integrated cir­

4Kx4 rom

Contextual Info: L S I LOGIC CORP f l l d Ë | S304Ô04 000DÔ3S S | LSI LO G IC C O R P O R A T IO N General Description The LSA2006 is a member of the 2-micron drawn, 1.4-micron effective HCMOS family of Structured Arrays offered by LSI Logic Corporation. These very high performance, Application Specific Integrated Cir­

te 2304

Contextual Info: LSI LO G IC C O R P O R A T IO N LSA2009 Two Micron HCA/IOS Structured Array TM 000978 lïJlliSiISP %WMëÊgMiÊÊM§$f$0$M. General Description The LSA2009 is a member of the 2-micron drawn, 1.4-micron effective HCMOS fam ily of Structured Arrays offered by LSI LOGIC Corporation. These very

CA914

Abstract: ca9140
Contextual Info: L S I LOGIC CORP fiï DE| S3DMflDM O D QDfl3 °T H f LSI LO G IC C O R P O R A T IO N Drr T -4 6 -1 3 -4 7 LSA2007 Tw o M icron HCM OS Structured A rra y General Description The LSA2007 is a member of the 2-micron drawn, 1.4-micron effective HCMOS family of Structured

Contextual Info: L S I LOGI C CORP Al D E I S30Mfl D4 GGQGfllT'? D ^ ' T‘- 4 6 - 13-47 LSA2002 Two Micron HCMOS Structured A rray LSI LO G IC C O R P O R A T IO N General Description The LSA2002 is a member of the 2-micron drawn, 1.4-micron effective HCMOS family of Structured

Contextual Info: L S I L OG I C CORP fil De 5304004 0000S43 4 | ' DfT •.T.-46-.13-47 LSA2008 Two Micron HCMOS Structured A rray LSI LOGIC CORPORATION PRELIMINARY General Description The LSA2008 is a member of the 2-micron drawn, (1.4-micron effective HCMOS family of Structured

No Turnaround RAM

Abstract: LSA2003 LSI Logic
Contextual Info: 5 LSI LOGIC C O R PO R A T IO N •¿-7 ' LSA 2003 tò*T w o M ic ro n H C M O S Structured A rra y 000976 G en e ra l D e s c rip tio n Arrays provide a high d e n sity o f logic fu n c tio n a lity w h ile m a in ta in in g the fle x ib ility of design and fa st

ILX554B

Abstract: 2048Pixels LSA200 ILX554 S2045 sony CCD LINEAR IMAGE SENSOR S2048 18 pixels
Contextual Info: ILX554B 2048-pixel CCD Linear Sensor B/W for Single 5V Power Supply Bar-code Reader Description The ILX554B is a rectangular reduction type CCD linear image sensor designed for bar code POS hand scanner and optical measuring equipment use. A built-in timing generator and clock-drivers ensure

Contextual Info: GFS2020A GFS2020A GFS2020A 1 6 X 4 CAM WITHOUT MASK GENERAL DESCRIPTION: THE GFS2020A MEGAFUNCTION IS A 16-WORD BY 4-BIT CONTENT ADDRESSABLE MEMORY CAM . THIS MEGAFUNCTION IS FUNCTIONALLY IDENTICAL TO THE FAIRCHILD 100142 EXCEPT THAT IT HAS SIXTEEN WORDS INSTEAD OF FOUR AND IT HAS NO MASK FUNCTION. FOR A DETAILED

Contextual Info: GFS2010A GFS2010A GFS2 01OA 8 X 4 CAM WITHOUT MASK G E N ERAL D E S C R I P T I O N : THE GFS2010A MEGAFUNCTION IS AN 8-WORD BY 4-BIT CONTENT ADDRESSABLE MEMORY CAM . THIS MKGAFUNCTION IS FUNCTIONALLY IDENTICAL TO THE FAIRCHILD 100142 EXCEPT THAT IT HAS EIGHT WORDS INSTEAD OF FOUR AND IT HAS NO MASK FUNCTION. FOR A DETAILED

LSA2000

Abstract: 74181 alu
Contextual Info: GFT1813A GFT1813A GFT1813A 32-BIT ALU GENERAL DESCRIPTION: THE GFT1813A MEGAFUNCTION IS LOGICALLY IDENTICAL TO THE TI 74181, EXCEPT IT OPERATES ON TWO 32-BIT WORDS. THE GPT1813A ARITHMETIC LOGIC UNIT ALU PERFORMS 16 LOGICAL OPERATIONS, AND USES A 32-BIT FAST CARRY-SELECT ADDER TO PERFORM 16

Contextual Info: GFB0220A GFB0220A GFB0220A 16-BIT CARRY-SELECT ADDER GENERAL D E S C R I P T I O N : THE GFB0220A USES A FAST CARRY-SELECT ALGORITHM TO PERFORM AN ADDITION OF TWO 16-BIT NUMBERS. PIN DIAGRAM: GFB0220A •GATES USED » 287 -AREA USED - 376 GATE LOCATIONS •PROPAGATION DELAY « 28 NS

TRANSISTOR a31

Abstract: magnitude comparator Transistor B29 transistor A19 P
Contextual Info: GFC2200A GFC2200A 32-BIT MAGNITUDE COMPARATOR GFC2200A GENERAL DESCRIPTION: THE GFC2200A IS A MAGNITUDE COMPARATOR. IT COMPARES TWO 32-BIT BINARY NUMBERS AND YIELDS THREE OUTPUTS {A>B, A<B„ AND A-B . PIN DIAGRAM: GFC2200A - GATES USED - 34 8 - AREA USED - 379 GATE

through data 4 a

Contextual Info: GFS0510A GFS0510A GFS0510A 16 X 4 FIFO FIRST-IN FIRST-OUT GENERAL DESCRIPTION: THE GFS0510A MEGAFUNCTION IS A 16 X 4 FIFO (FIRST-IN FIRST-OUT) . IT HAS SEPARATE READ (RDN) AND WRITE (WRN) CLOCKS WHICH ARE COMPLETELY INDEPENDENT <CAN BE ASYCHRONOUS) . THIS FIFO USES A "FALL-THROUGH“ ALGORITHM IN WHICH

P08 transistor

Abstract: 8x8 booth multiplier
Contextual Info: GFB2000A GFB2000A GFB2000A 8X8 2 'S COMPLEMENT MULTIPLIER GENERAI. DESCRIPTION: THE GFB2000A MEGAFUNCTION 15 AN 8-BY-8 2 'S COMPLEMENT MULTIPLIER WHICH GENERATES A 16-BIT PRODUCT. BY USING A MODIFIED BOOTH ALGORITHM, THIS MEGAFJNCTION GIVES A REASONABLE SPEED AND GATE COUNT.

Contextual Info: cQ ^p f'C LSI LO G IC C O R P O R A T IO N LSA 2004 c T w o M icro n H CM O S S tru ctu red A r r a y TM 000977 General Description Arrays provide a high density of logic fun ctionality while m aintaining the fle xib ility of design and fast turn-around of metal mask programmable logicarrays. The use of dual layer metal interconnect

Am29501

Abstract: BM05 05GN amd 2900 transistor BMO 123
Contextual Info: GFA5010A GFA5010A GFA5010A MULTI-PORT PIPELINED PROCESSOR GENERAL DESCRIPTION: THE GFA5010A IS DESIGNED TO BE FULLY COMPATIBLE WITH THE AM29501 BYTE—SLICE MULTI-PORT PIPELINED PROCESSOR, EXCEPT THAT THE I/O'S ARE DIFFERENT SEE PAGE 2 OF 4 FOR A DESCRIPTION OF THE ENHANCEMENTS TO THE AM29501 . FOR A DETAILED

5 pin ic ARB

Abstract: amd 2900
Contextual Info: GFA0040A GFA0040A GFA0040A STATUS AND SHIFT CONTROL UNIT GENERAL DESCRIPTION : THE GFA004 0A IS DESIGNED TO BE FUNCTIONALLY IDENTICAL TO THE AM2904 f ALTHOUGH THE I/O'S ARE DIFFERENT SEE PAGE 2 OF 3 FOR THE ENHANCEMENTS TO THE AM2904 . FOR A DETAILED FUNCTIONAL DESCRIPTION SEE THE AMD 2900 DATA BOOK.

LSA2004

Contextual Info: LSI L O G IC C O R P O R A T IO N 000977 LS A 2 0 0 4 c T w o M icron H CM O S Stru ctu red A r r a y TM General Description Arrays provide a high d e n sity o f lo g ic fu n c tio n a lity w hile m a in ta in in g the fle x ib ility o f design and fast turn-around o f m etal m ask program m able logicarrays. The use o f dual layer m etal in te rco n n e ct