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    LS 00 LOGIC GATES Search Results

    LS 00 LOGIC GATES Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TB67H481FTG Toshiba Electronic Devices & Storage Corporation Stepping and Brushed Motor Driver /Bipolar Type / Vout(V)=50 / Iout(A)=3.0 / IN input type / VQFN32 Visit Toshiba Electronic Devices & Storage Corporation
    TLP5702H Toshiba Electronic Devices & Storage Corporation Photocoupler (Gate Driver Coupler), High-Topr / IGBT driver, 5000 Vrms, SO6L Visit Toshiba Electronic Devices & Storage Corporation
    TLP5705H Toshiba Electronic Devices & Storage Corporation Photocoupler (Gate Driver Coupler), High-Topr / IGBT driver, 5000 Vrms, SO6L Visit Toshiba Electronic Devices & Storage Corporation
    7UL2T125FK Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), Buffer, SOT-765 (US8), -40 to 85 degC Visit Toshiba Electronic Devices & Storage Corporation
    7UL2T126FK Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), Buffer, SOT-765 (US8), -40 to 85 degC Visit Toshiba Electronic Devices & Storage Corporation

    LS 00 LOGIC GATES Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    schmitt trigger 4093

    Abstract: D16841 4017 decade counter 1-of-10 dual differential line driver 88c30 HC 4093 4013 astable 16-LINE TO 4-LINE PRIORITY ENCODERS 7 segment 40192 88c29 4011 astable
    Text: Revised April 1999 Functional Selection Table 1999 Fairchild Semiconductor Corporation MS500117.prf www.fairchildsemi.com Functional Selection Table February 1998 Gates Function CROSSVOLT Device Leads FACT FAST FASTr ALS AS LS S TTL ABT VCX LCX LVX LVT LVQ AC ACT


    Original     		PDF MS500117 schmitt trigger 4093 D16841 4017 decade counter 1-of-10 dual differential line driver 88c30 HC 4093 4013 astable 16-LINE TO 4-LINE PRIORITY ENCODERS 7 segment 40192 88c29 4011 astable

    als86

    Abstract: No abstract text available
    Text: AVG DDi Semiconductors CO Technical Data 00 DV74LS86 DV74ALS86 Quad 2-lnput Exclusive OR Gates N Suffix Plastic DIP AVG-001 Case This device contains four independent gates, each of which performs the logic exclusive-OR function. • AVG’s LS operates over extended Vcc from 4.5 to 5.5 V


    OCR Scan     		PDF DV74LS86 DV74ALS86 AVG-001 AVG-002 ALS86 1-800-AVG-SEMI DV74LS86, DV74ALS86 TD1D11Ã

    als86

    Abstract: LS86 LS 00 Logic Gates low propagation delay gates
    Text: AVG Semiconductors DDT CO T e ch n ica l Data 00 DV74LS86 DV74ALS86 Quad 2-Input Exclusive OR Gates N Suffix Plastic DIP AVG-001 Case This device contains four independent gates, each of which perform s the logic exclusive-O R function. • AVG’s LS operates over extended Vcc from 4.5 to 5.5 V


    OCR Scan     		PDF DV74LS86 DV74ALS86 AVG-001 AVG-002 ALS86 1-800-AVG-SEMI DV74LS86, DV74ALS86 LS86 LS 00 Logic Gates low propagation delay gates

    ot 112

    Abstract: SN54ALS133 SN74ALS133 ALS133 Y175
    Text: SN74ALS133, SN54ALS133 13-INPUT POSITIVE-NAND GATES D2661, APRIL 1982-R E V IS E D M AY 1986 Package Options Include Plastic "Sm all Outline" Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-m il DIPs • SN 54A LS 133 . . . J PACKAGE


    OCR Scan     		PDF SN74ALS133, SN54ALS133 13-INPUT D2661, 1982-REVISED 300-mil SN74ALS133 ALS133 ot 112 Y175

    74HCoo

    Abstract: TTL 74HC00 74LS00 pinout pin diagram of 74ls00 74HC00 GD74HC00 logic symbol 74LS00 74hc00 and gates pin configuration logic symbol 74LS00 74LS00 gate diagram
    Text: GD54/74HC00, GD54/74HCT00 QUAD 2-INPUT NAND GATES General Description These devices are identical in pinout to the 54/74LS 00. They contain four independent 2-input NAND gates. These devices are characterized for operation over wide temperature ranges to meet in­


    OCR Scan     		PDF GD54/74HC00, GD54/74HCT00 54/74LS00. GD74HCT00 GD54HCT00 74HCoo TTL 74HC00 74LS00 pinout pin diagram of 74ls00 74HC00 GD74HC00 logic symbol 74LS00 74hc00 and gates pin configuration logic symbol 74LS00 74LS00 gate diagram

    LS00

    Abstract: ALS00a
    Text: AVG DDi“ Sem iconductors Technical Data O o DV74LS00 DV74ALS00A Quad 2-Input NAND Gate This device contains four independent gates, each of which performs the logic NAND function. N Suffix Plastic DIP AVG-001 Case • • AVG’s LS operates over extended Vcc from 4.5 to 5.5 V


    OCR Scan     		PDF DV74LS00 DV74ALS00A AVG-001 AVG-002 ALS00A 500i2 DV74LS00, -800-AVG-SEMI LS00

    ls 7400

    Abstract: 7400 signetics TTL TTL LS 7400 7400 ls 7400 pin configuration TTL 7400 propagation delay 74l500 74LS00 signetics 74ls00 tr tf 74LS00 function table
    Text: Signetìcs I 7400, LS00, S00 Gates Quad Two-Input NAND Gate Product Specification Logic Products TY PE T Y P IC A L PR O P A G A TIO N D E LA Y T Y P IC A L SU P P LY C U R R E N T TO T A L 9ns 8m A 74LS00 9.5ns 1.6mA 74SOO 3ns 15m A 7400 ORDERING CODE C O M M E R C IA L RA NG E


    OCR Scan     		PDF 74LS00 74SOO N7400N, N74LS00N, N74S00N N74LS00D, N74S00D 10Sul 10LSul WF07570S ls 7400 7400 signetics TTL TTL LS 7400 7400 ls 7400 pin configuration TTL 7400 propagation delay 74l500 74LS00 signetics 74ls00 tr tf 74LS00 function table

    Untitled

    Abstract: No abstract text available
    Text: GD54/74HC00, GD54/74HCT00 QUAD 2-INPUT NAND GATES General Description These devices are identical in pinout to the 54/74LS00. They contain four independent 2-input NAND gates. These devices are characterized for operation over wide temperature ranges to meet in­


    OCR Scan     		PDF GD54/74HC00, GD54/74HCT00 54/74LS00.

    MC815

    Abstract: MC900 DSP56302 MC915
    Text: DUAL3-INPUT GATES \ MC915 • MC815 M R T L MC900/800 series Available in TO-100 Metal Can, Add " G " Suffix. Available in TO-91 Flat Package, Add "F" Suffix. Two 3-input positive logic NO R gates in a single package may be used independently, paralfeted for increasing the num­


    OCR Scan     		PDF MC900/800 MC915 MC815 O-100 1n3063 MC915 MC815 AA0476 DSP56302 MC900

    Untitled

    Abstract: No abstract text available
    Text: AVG Semiconductors DDi Technical Data DV74LS86 DV74ALS86 Quad 2-Input Exclusive OR Gates SÄ W This device contains four independent gates, each of which performs the logic exclusive-OR function. I I • AVG’s LS operates over extended Vcc from 4.5 to 5.5 V


    OCR Scan     		PDF DV74LS86 DV74ALS86 AVG-001 AVG-002 ALS86 1-800-AVG-SEMI TD1D11Ã DV74LS86,

    Untitled

    Abstract: No abstract text available
    Text: LSOO LS04 LS10 LS20 LS30 Positive-NAND Gates, Hex Inverters PIN-OUT AND LOGIC DIAGRAMS LS04 HEX INVERTER LSOO QUADRUPLE 2-INPUT NAND GATE 11 10 12 Vcc 6A 6Y 5A 5Y 4A 4Y 03 OD ED D3 El] 13 14 1 Ip W 1 2 Uj[f] T| 0 Ü ] GDCÌ 0 0 ( 1 ] 0 G D 00 CD 1A 1Y 2A 2Y 3A 3Y GND


    OCR Scan     		PDF

    IN4106

    Abstract: CAG10A CAG10 CAG10B CAG10C CAG30 TELEDYNE CRYSTALONICS
    Text: FET ANALOG GATES These circ u its can be used an yw h ere a sw itch is needed fo r curre nts up to 100 m A and voltages up to ± 10V. The lo w e r the Ron, the higher the peak c u rre n t h a n d lin g a b ility . A ll e xce p t th e C A G 6 operate d ire c tly fro m D T L o r T T L lo gic w ith o u t special biasing.


    OCR Scan     		PDF CAG30 140kHz 140Hz 200pfd CAG10 IN4106 IN4106 CAG10A CAG10B CAG10C TELEDYNE CRYSTALONICS

    Untitled

    Abstract: No abstract text available
    Text: AVG Semiconductors DDi Technical Data ro DV74LS22 DV74ALS22B Dual 4-Input NAND Gates with Open Collector Outputs io N Suffix Plastic DIP AVG-001 Case This device contains two independent gates, each of which performs the logic NAND function. The opencollector outputs require external pull-up resistors for


    OCR Scan     		PDF DV74LS22 DV74ALS22B AVG-001 AVG-002 ALS22B DV74LS22, DV74LS22B 1-800-AVG-SEMI

    TTL 7411

    Abstract: PIN CONFIGURATION 7410 74LS11 function table TTL LS 7411 74 LS 00 Logic Gates LS 7411 74LS10 pin configuration TTL 7410 TTL 7410 AND propagation delay PIN CONFIGURATION 74ls10
    Text: Signetics I 7410, 7411, LS10, LS11, S10, S11 Gates Logic Products Triple Three-Input NAND '10 , AND ('11) Gates Product Specification I TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7410 9ns 6mA 74LS10 10ns 1.2mA 74S10 3ns 12mA 7411 10ns 11mA


    OCR Scan     		PDF 74LS10 74S10 74LS11 74S11 N7410N, N74LS10N, N74S10N N7411N, N74LS11N, N74S11N TTL 7411 PIN CONFIGURATION 7410 74LS11 function table TTL LS 7411 74 LS 00 Logic Gates LS 7411 74LS10 pin configuration TTL 7410 TTL 7410 AND propagation delay PIN CONFIGURATION 74ls10

    TTL 74HC00

    Abstract: 74LS00 TTL TTL 74ls00 74LS00 gate diagram 74ls00 74LS00 function table pin configuration logic symbol 74LS00 logic symbol 74LS00 74HC00 5V 74HC00
    Text: GD54/74HC00, GD54/74HCT00 QUAD 2-INPUT NAND GATES General Description These devices are identical in pinout to the 54/74LS00. They contain four independent 2-input NAND gates. These devices are characterized for operation over wide temperature ranges to meet in­


    OCR Scan     		PDF GD54/74HC00, GD54/74HCT00 54/74LS00. GD74HCT00 GD54HCT00 D0Q457Q TTL 74HC00 74LS00 TTL TTL 74ls00 74LS00 gate diagram 74ls00 74LS00 function table pin configuration logic symbol 74LS00 logic symbol 74LS00 74HC00 5V 74HC00

    ALS08

    Abstract: LS08
    Text: AVG Semiconductors DDi Technical Data 00 DV74LS08 DV74ALS08 QUAD 2-INPUT AND GATE This device contains four indpendent 2-input AND gates. AVG’s LS operates over extended Vcc from 4.5 to 5.5 V AVG’s LS and ALS both have guaranteed DC and AC specification over full temperature and Vcc range


    OCR Scan     		PDF AVG-001 AVG-002 ALS08 DV74LS08, DV74ALS08 1-800-AVG-SEMI LS08

    74LS00 pinout

    Abstract: GD74HC00 pin configuration logic symbol 74LS00 logic symbol 74LS00 74HC00 5V 74HC00 74hc00 and gates TTL 74HC00 74HC GD54HC00
    Text: GDS4/74HC00, GD54/74HCT00 QUAD 2-INPUT NAND GATES General Description These devices are identical in pinout to the 54/74LS 00. They contain four independent 2-input NAND gates. These devices are characterized for operation over wide temperature ranges to meet in­


    OCR Scan     		PDF GD54/74HC00, GD54/74HCT00 54/74LS00. GD74HCT00 GD54HCT00 74LS00 pinout GD74HC00 pin configuration logic symbol 74LS00 logic symbol 74LS00 74HC00 5V 74HC00 74hc00 and gates TTL 74HC00 74HC GD54HC00

    SCHMITT-TRIGGER

    Abstract: 312H texas instruments circuit diagram CMOS Texas Instruments Incorporated 4 inputs positive OR gates HC03 y4nc
    Text: HIGH-SPEED CMOS LOGIC TYPES SN 54H C 7003, S N 74H C 7003 QUADRUPLE POSITIVE-NAND GATES W ITH SCHM ITT TRIGGER INPUTS AND OPEN-DRAIN OUTPUTS D2831, M AH CH 1984 • O p e ra tio n fr o m V e ry S lo w T r a n s itio n s • T e m p e ra tu re -C o m p e n s a te d T h re s h o ld L e v e ls


    OCR Scan     		PDF SN54HC7003, SN74HC7003 D2831, SN54HC7003 SCHMITT-TRIGGER 312H texas instruments circuit diagram CMOS Texas Instruments Incorporated 4 inputs positive OR gates HC03 y4nc

    74LS14 not gate

    Abstract: 74LS14 74ls14 ttl ttl 74ls14 74LS14 DATA LS14 74LS13 TTL Schmitt-Trigger Inverters 751A-02 LS13
    Text: MOTOROLA SN54/74LS13 SN54/74LS14 SCHMITT TRIGGERS DUAL GATE/HEX INVERTER The SN 54LS /74LS 13 and S N 54LS /74LS 14 contain logic gates/inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into


    OCR Scan     		PDF SN54LS/74LS13 SN54LS/74LS14 SN54/74LS13 SN54/74LS14 74LS14 not gate 74LS14 74ls14 ttl ttl 74ls14 74LS14 DATA LS14 74LS13 TTL Schmitt-Trigger Inverters 751A-02 LS13

    74LS series logic gates

    Abstract: 74LS series logic gates 3 input or gate MN74HC32 85ti buffer 74ls series logic gates MN74HC32S
    Text: MN74HC32/MN74HC32S High-Speed CMOS Logic MN74HC Series MN74HC32 MN74HC32S Quad 2 -Input OR Gates • Description P -1 M N 74H C32/M N 74H C32S contain four 2-input positive isolation O R gate circuits. Adoption o f a silicon gate CMOS process has resulted in low


    OCR Scan     		PDF MN74HC MN74HC32/MN74HC32S MN74HC32 MN74HC32S MN74HC32/MN74HC32S 10-inputs 74LS series logic gates 74LS series logic gates 3 input or gate 85ti buffer 74ls series logic gates MN74HC32S

    Untitled

    Abstract: No abstract text available
    Text: üiLattice ispLSI and pLSI 1048 i ! : : i i c o r p o ° a ntfon’0r High-Density Programmable Logic Functional Block Diagram Features • HIGH-DENSITY PROGRAMMABLE LOGIC — 8000 PLD Gates — — — — 96 I/O Pins, Ten Dedicated Inputs 288 Registers High-Speed Global Interconnects


    OCR Scan     		PDF 0212-8Q 1048-80LQ 120-Pin 1048-70LQ 1048-50LQ

    74LS series logic gates 3 input or gate

    Abstract: MN74HC00S 74LS series logic gates MN74HC00
    Text: MN74HCOO/MN74HCOOS High-Speed CMOS Logic MN74HC Series MN74HCOO/MN74HCOOS Quad 2 -Input NAND Gates • Description P-1 M N 74H C 00/M N 74H C 00S contain four 2-input pcsitive isolation N A N D gate circuits. A doption o f a silicon gate CMOS process has resulted in low


    OCR Scan     		PDF MN74HC MN74HCOO/MN74HCOOS MN74HC00/MN74HC00S 10-inputs 74LS series logic gates 3 input or gate MN74HC00S 74LS series logic gates MN74HC00

    TTL LS 7413

    Abstract: 74 LS 00 Logic Gates schmitt trigger 7413 ls 7413 n
    Text: 7413, LS13 Signetics Gates Dual 4-Input NAND Schmitt Trigger Product Specification Logic Products DESCRIPTION T h e '1 3 contains tw o 4-input N A N D gates which accept standard T T L input signals and provide standard T T L output levels. Th ey are capable of transforming


    OCR Scan     		PDF OP01670S P016B0S TTL LS 7413 74 LS 00 Logic Gates schmitt trigger 7413 ls 7413 n

    Untitled

    Abstract: No abstract text available
    Text: 74LS260, S260 Signetics Gates Dual 5-Input NOR Gate Product Specification Logic Products TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT TOTAL 74LS260 9ns 4 mA 74S260 4ns 22mA FUNCTION TABLE OUTPUT INPUTS A B c E Y H X X X X L X H X X X L X X H X X


    OCR Scan     		PDF 74LS260, 74LS260 74S260 SO-14 N74S260N, N74LS260N N74LS260D, N74S260D 74Srting 1N916,