LH534P00A Search Results

Contextual Info: LH534P00A CMOS 4M 512K x 8/256K x 16 MROM FEATURES PIN CONNECTIONS • 524,288 words x 8 bit organization (Byte mode) 262,144 words x 16 bit organization (Word mode) • Access time: 120 ns (MAX.) • Power consumption: Operating: 357.5 mW (MAX.) Standby: 550 (iW (MAX.)

Contextual Info: LH534P00A FEATURES • 524,288 words x 8 bit organization Byte mode 262,144 words x 16 bit organization (Word mode) • Access time: 120 ns (MAX.) • Power consumption: Operating: 357.5 mW (MAX.) Standby: 550 |iW (MAX.) • Static operation • TTL compatible I/O

48-PIN

Contextual Info: LH534P00A FEATURES • 524,288 words x 8 bit organization Byte mode 262,144 words × 16 bit organization (Word mode) • Access time: 120 ns (MAX.) • Power consumption: Operating: 357.5 mW (MAX.) Standby: 550 µW (MAX.) • Static operation • TTL compatible I/O

Contextual Info: LH534P00A CMOS 4M 512K x 8/256K x 16 MROM FEATURES PIN CONNECTIONS • 524,288 words x 8 bit organization (Byte mode) 262,144 words x 16 bit organization (Word mode) 40-PIN DIP 40-PIN SOP TOP VIEW s A i? □ • Power consumption: Operating: 357.5 mW (MAX.)

lh5s4

Abstract: lh5348 LH5s lh5s47xx 48-TSOP LH53H4100D LH53H4100N lh534y00d 48TSOP sharp mask rom
Contextual Info: NEW PRODUCT INFORMATION SHARP LH53 H4100 • Description High-speed 4M-bit Mask-Programmable ROM ■ Pin Connections The LH53H4100D/N User's No. ! LH5H41XX is a CMOS 4M-bit mask-programmable ROM organized as 524 288 X 8 bits. It is fabricated using sillicon-gate CMOS process technology.

lh57257

Abstract: IR2E31 IR2E01 IR2C07 IR2E27 IR2E24 IR2E19 IR2E31A IR3n06 IR2E02
Contextual Info: Index Model No. ARM7D CPU Core Bi-CMOS 1 27 40,42 _ _ CMOS CMOS CMOS CMOS CMOS 4A 5A 8 A AH D ID1 Series ID2 Series 40,42 40.42 40,42 40,42 40 B ü.’1*"! 14,15 14 m IR2339 IR2403 IR2406 IR2406G IR2410 IR2411 IR2415 IR2419 IR2420 IR2422 IR2425 IR2429

LH231G

Abstract: lh5348 LH538b LH2326 lh5s4 LHMN5 lh5359 lh5348xx lh537 LH235
Contextual Info: MEMORIES ★Under development • M ask ROMs SlpÉHRfi Bonflgmllan jvorai x d m i NMOS <"^g|g|ï|ïi£- User1* No. sssysr Sllpjiijp 1 currant mA MAX. ■ Paefcagfe ft- • 64k 8k x 8 LH2389D LH2369XX 200 60 5 ± 10% 28DIP 128k 16k x 8 LH23128D LH2326XX 200

flash 64m

Contextual Info: MEMORIES Mask ROMs C a p a c ity Access time C o nfig u ra tio n 120ns 100ns 80ns 150ns 256kj I 32k x 8 ] LH53259 12k I 64k x 8 LH53517 128k x 8 LH530800A LH531V00 1M LH531024 64k x 16 i LH532100B-1 256k x 8 ! LH532100B 2M JEDEC standard EPROM pinout 128k x 161

lh5348

Abstract: TSOP032-P-0820 lh5s4 flash memory sop 32-pin lh5348xx lh5s47xx
Contextual Info: NEW PRODUCT INFORMATION LH53V4R00 LH53V4R00-2 • Low-Voltage • High-Speed 4M-bit Mask-Programmable ROM Description Pin Connection T he L H 5 3 V 4 R 0 0 N /T , L H 5 3 V 4 R 0 0 N /T -2 U s e r's N o. : LH5V4RXX is a CM O S 4M -bit m ask-program m able ROM

LH534

Abstract: 48-PIN A10C A15C A17C
Contextual Info: LH 534P00A FEATURES CMOS 4M 512K x 8/256K x 16 M ask-Program m able ROM PIN CONNECTIONS • 524,288 words x 8 bit organization (Byte mode) 40-PIN DIP 40-PIN SOP TOP VIEW f- . 262,144 words x 16 bit organization (Word mode) A i7C 1• a 7[= 2 • Access time: 120 ns (MAX.)

48 tsop flash pinout

Abstract: LH23512
Contextual Info: MEMORIES Mask ROMs ^Under development Capacity Pinout Model No. Configuration Access time ns 55 1 64k !- 1 8k x 8 128k 16k x ! 256k 32k x 8 |- -) [ 512k 64k x 8 b — I 80 100 120 150 200 Package 250 500 □ LH2369 28 LH23255 28 □ LH53259 28 28 38(1)

sharp mask rom

Abstract: cd rom 40 pinout lh5348 lh5s4 LH5S
Contextual Info: NEW PRODUCT INFORMATION SHARP LH53H4000 • Description The LH53H4000D/N User's No. : LH5H40XX is a CMOS 4M-bit mask-programmable ROM organized as 524 288 X 8 bits (Byte mode) or 262 144 X 16 bits (Word mode) that can be selected by BYTE input pin. ■ Features

lh5348

Abstract: lh5s4 lh5348xx sharp mask rom LH534A00T LH5s LH534B00T 40-DIP
Contextual Info: NEW PRODUCT INFORMATION SHARP LH53H4100 • High-speed 4M-bit Mask-Programmable ROM ■ Description Pin Connections The LH53H4100D/N User's No. ! LH5H41XX is a CMOS 4M-bit mask-programmable ROM organized as 524 288 X 8 bits. It is fabricated using sillicon-gate CMOS process technology.

lh5348

Abstract: lh5348xx sharp mask rom lh5s4
Contextual Info: NEW PRODUCT INFORMATION SHARP LH53 H 4100 • High-speed 4M-bit Mask-Programmable ROM ■ Description Pin Connections The LH53H4100D/N User’s No. : LH5H41XX is a CMOS 4M-bit mask-programmable ROM organized as 524 288 X 8 bits. It is fabricated using sillicon-gate CMOS process technology.