L3840
Abstract: L5568 XL78C800 L1S24 L5760 L6240 ls376 L-1344 L6354 78c30
Text: R OHN CORP/ EXEL NELECS 3SE • 7ÖET014 0001353 'r'a b 1°1 07 M ICROELECTRONICS ExetUtnc» D fo E* S ■ REM XL78C800 Multi-Level E2PLDs PIN CO NFIGU RATIO N FEATURES ■ 600-800 Gate Equivalent Logic Com plexity 24 Pin Skinny DIP Type "P 3” Package ■
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ET014
XL78C800
L3840
L5568
XL78C800
L1S24
L5760
L6240
ls376
L-1344
L6354
78c30
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L5952 equivalent
Abstract: L5952 L1824 L2976 L3840 L2592 L4032 IJ264 L5472
Text: MICROELECTRONICS XL78C800 E xctllV K i in E2 Multi-Level E2PLDs PIN CONFIGURATION FEATURES • 600-800 Gate Equivalent Logic Complexity 24 Pin Skinny DIP Type "P3" Package ■ Industry-Standard Data I/O ABEL PLD Design Tool Compatibility CLK/I ■ Advanced ERASIC Architecture
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OCR Scan
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XL78C800
64-way
L5952 equivalent
L5952
L1824
L2976
L3840
L2592
L4032
IJ264
L5472
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L5472
Abstract: L2688 L5568
Text: r x / i r * ! MICROELECTRONICS XL78C800 Multi-Level E2PLDs PIN CONFIGURATION FEATURES • ■ ■ CLK/I [ Advanced ERASIC Architecture — True gate array style logic integration — From 1 to 42 internal logic levels without using a pin — Eliminates 2-level logic restriction of
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OCR Scan
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XL78C800
L5472
L2688
L5568
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