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    74AVCH1T45

    Abstract: No abstract text available
    Text: 74AVCH1T45 Dual-supply voltage level translator/transceiver; 3-state Rev. 4 — 3 August 2012 Product data sheet 1. General description The 74AVCH1T45 is a single bit, dual supply transceiver that enables bidirectional level translation. It features two 1-bit input-output ports A and B , a direction control input (DIR)


    Original     		PDF 74AVCH1T45 74AVCH1T45

    Untitled

    Abstract: No abstract text available
    Text: 74LVC1G14 Single Schmitt-trigger inverter Rev. 12 — 6 August 2012 Product data sheet 1. General description The 74LVC1G14 provides the inverting buffer function with Schmitt-trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free


    Original     		PDF 74LVC1G14 74LVC1G14

    application note tssop5 nxp

    Abstract: No abstract text available
    Text: 74LVC1G06 Inverter with open-drain output Rev. 10 — 29 June 2012 Product data sheet 1. General description The 74LVC1G06 provides the inverting buffer. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.


    Original     		PDF 74LVC1G06 74LVC1G06 application note tssop5 nxp

    Untitled

    Abstract: No abstract text available
    Text: 74LVC1G08 Single 2-input AND gate Rev. 9 — 9 December 2011 Product Specification 1. General description The 74LVC1G08 provides one 2-input AND function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications.


    Original     		PDF 74LVC1G08 74LVC1G08 771-LVC1G08GWDG125 74LVC1G08GW/DG

    marking VU SOT363

    Abstract: No abstract text available
    Text: 74LVC1G11 Single 3-input AND gate Rev. 7 — 4 July 2012 Product data sheet 1. General description The 74LVC1G11 provides a single 3-input AND gate. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.


    Original     		PDF 74LVC1G11 74LVC1G11 marking VU SOT363

    Marking code V7

    Abstract: No abstract text available
    Text: 74LVC2G00 Dual 2-input NAND gate Rev. 11 — 22 June 2012 Product data sheet 1. General description The 74LVC2G00 provides a 2-input NAND gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.


    Original     		PDF 74LVC2G00 74LVC2G00 Marking code V7

    ep4cgx30f484

    Abstract: EP4CE115 CYIV-5V1-1 EP4CGX EP4CE55 EP4CE15 sigma delta lcd screen lvds 40 pin diagram ep4ce22 ep4ce40
    Text: Cyclone IV Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com CYIV-5V1-1.5 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other


    Original     		PDF

    74AUP1G80

    Abstract: 74AUP1G80GF 74AUP1G80GM 74AUP1G80GW MO-203
    Text: 74AUP1G80 Low-power D-type flip-flop; positive-edge trigger Rev. 01 — 20 October 2006 Product data sheet 1. General description The 74AUP1G80 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.


    Original     		PDF 74AUP1G80 74AUP1G80 74AUP1G80GF 74AUP1G80GM 74AUP1G80GW MO-203

    74AUP1G19GM

    Abstract: 74AUP1G19GW JESD22-A114E
    Text: 74AUP1G19 Low-power 1-of-2 decoder/demultiplexer Rev. 01 — 13 August 2008 Product data sheet 1. General description The 74AUP1G19 provides a 1-of-2 decoder/demultiplexer with a common output enable. It buffers the data on input pin A and passes it either to output pin 1Y true or 2Y


    Original     		PDF 74AUP1G19 74AUP1G19 74AUP1G19GM 74AUP1G19GW JESD22-A114E

    74AUP2G125

    Abstract: 74AUP2G125DC 74AUP2G125GT JESD22-A114E JESD78
    Text: 74AUP2G125 Low-power dual buffer/line driver; 3-state Rev. 05 — 2 February 2009 Product data sheet 1. General description The 74AUP2G125 provides the dual non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input nOE . A HIGH level at pin nOE


    Original     		PDF 74AUP2G125 74AUP2G125 74AUP2G125DC 74AUP2G125GT JESD22-A114E JESD78

    74AUP1G126

    Abstract: 74AUP1G32 JESD22-A114E 74AUP1T1326
    Text: 74AUP1T1326 Low-power dual supply buffer/line driver; 3-state Rev. 01 — 20 January 2009 Product data sheet 1. General description The 74AUP1T1326 is a high-performance, low-power, low-voltage, single-bit, dual supply buffer/line driver with output enable circuitry.


    Original     		PDF 74AUP1T1326 74AUP1T1326 74AUP1G32 74AUP1G126. 74AUP1G126 JESD22-A114E

    74LVC1G04

    Abstract: 74LVC1G04GF 74LVC1G04GM 74LVC1G04GV 74LVC1G04GW JESD22-A114E MO-203
    Text: 74LVC1G04 Single inverter Rev. 08 — 27 April 2009 Product data sheet 1. General description The 74LVC1G04 provides one inverting buffer. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.


    Original     		PDF 74LVC1G04 74LVC1G04 74LVC1G04GF 74LVC1G04GM 74LVC1G04GV 74LVC1G04GW JESD22-A114E MO-203

    74LVC1G06

    Abstract: 74LVC1G06GF 74LVC1G06GM 74LVC1G06GV 74LVC1G06GW JESD22-A114E
    Text: 74LVC1G06 Inverter with open-drain output Rev. 07 — 12 July 2007 Product data sheet 1. General description The 74LVC1G06 provides the inverting buffer. Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment.


    Original     		PDF 74LVC1G06 74LVC1G06 74LVC1G06GF 74LVC1G06GM 74LVC1G06GV 74LVC1G06GW JESD22-A114E

    74AVCH2T45

    Abstract: 74AVCH2T45DC 74AVCH2T45GT JESD22-A114E
    Text: 74AVCH2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state Rev. 03 — 6 May 2009 Product data sheet 1. General description The 74AVCH2T45 is a dual bit, dual supply transceiver that enables bidirectional level translation. It features two data input-output ports nA and nB , a direction control input


    Original     		PDF 74AVCH2T45 74AVCH2T45 74AVCH2T45DC 74AVCH2T45GT JESD22-A114E

    74LVC2G126

    Abstract: 74LVC2G126DC 74LVC2G126DP 74LVC2G126GD 74LVC2G126GM 74LVC2G126GT JESD22-A114E MO-187
    Text: 74LVC2G126 Dual bus buffer/line driver; 3-state Rev. 08 — 5 May 2008 Product data sheet 1. General description The 74LVC2G126 is a dual non-inverting buffer/line driver with 3-state outputs. Each 3-state output is controlled by an output enable input pin nOE . A LOW-level at pin nOE


    Original     		PDF 74LVC2G126 74LVC2G126 74LVC2G126DC 74LVC2G126DP 74LVC2G126GD 74LVC2G126GM 74LVC2G126GT JESD22-A114E MO-187

    74AUP2G240

    Abstract: 74AUP2G240DC 74AUP2G240GT JESD22-A114E JESD78
    Text: 74AUP2G240 Low-power dual inverting buffer/line driver; 3-state Rev. 03 — 7 April 2009 Product data sheet 1. General description The 74AUP2G240 provides the dual inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input nOE . A HIGH level at pin nOE


    Original     		PDF 74AUP2G240 74AUP2G240 74AUP2G240DC 74AUP2G240GT JESD22-A114E JESD78

    74LVC2G241

    Abstract: 74LVC2G241DC 74LVC2G241DP 74LVC2G241GD 74LVC2G241GM 74LVC2G241GT JESD22-A114E
    Text: 74LVC2G241 Dual buffer/line driver; 3-state Rev. 09 — 10 June 2008 Product data sheet 1. General description The 74LVC2G241 is a dual non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE:


    Original     		PDF 74LVC2G241 74LVC2G241 74LVC2G241DC 74LVC2G241DP 74LVC2G241GD 74LVC2G241GM 74LVC2G241GT JESD22-A114E

    74LVC1G58

    Abstract: 74LVC1G58GF 74LVC1G58GM 74LVC1G58GV 74LVC1G58GW JESD22-A114E marking code 5
    Text: 74LVC1G58 Low-power configurable multiple function gate Rev. 04 — 27 April 2009 Product data sheet 1. General description The 74LVC1G58 provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,


    Original     		PDF 74LVC1G58 74LVC1G58 74LVC1G58GF 74LVC1G58GM 74LVC1G58GV 74LVC1G58GW JESD22-A114E marking code 5

    EP20K100E

    Abstract: EP20K600E
    Text: Using Selectable I/O Standards in APEX 20KE, APEX 20KC & MAX 7000B Devices October 2001, ver. 2.1 Introduction Application Note 117 High-performance, low-voltage I/O standards have been introduced to keep pace with increasing clock speeds, higher data rates, and new


    Original     		PDF 7000B EP20K100E EP20K600E

    74LVC2G125

    Abstract: 74LVC2G125DP V125
    Text: INTEGRATED CIRCUITS DATA SHEET 74LVC2G125 Dual bus buffer/line driver; 3-state Product specification 2003 Mar 10 Philips Semiconductors Product specification Dual bus buffer/line driver; 3-state 74LVC2G125 FEATURES DESCRIPTION • Wide supply voltage range from 1.65 to 5.5 V


    Original     		PDF 74LVC2G125 74LVC2G125 SCA75 613508/01/pp16 74LVC2G125DP V125

    dhvqfn14 footprint

    Abstract: 74ALVC00 74ALVC00BQ 74ALVC00D 74ALVC00PW DHVQFN14 TSSOP14 sot762 footprint SOT762-1 AN01026
    Text: INTEGRATED CIRCUITS DATA SHEET 74ALVC00 Quad 2-input NAND gate Product specification Supersedes data of 2003 Feb 06 2003 May 14 Philips Semiconductors Product specification Quad 2-input NAND gate 74ALVC00 FEATURES DESCRIPTION • Wide supply voltage range from 1.65 to 3.6 V


    Original     		PDF 74ALVC00 74ALVC00 SCA75 613508/02/pp16 dhvqfn14 footprint 74ALVC00BQ 74ALVC00D 74ALVC00PW DHVQFN14 TSSOP14 sot762 footprint SOT762-1 AN01026

    MDB105

    Abstract: sot762 footprint MNA423 74ALVC74 74ALVC74BQ 74ALVC74D 74ALVC74PW DHVQFN14 TSSOP14 2SD92
    Text: INTEGRATED CIRCUITS DATA SHEET 74ALVC74 Dual D-type flip-flop with set and reset; positive-edge trigger Product specification Supersedes data of 2003 Jan 24 2003 May 26 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset;


    Original     		PDF 74ALVC74 74ALVC74 JESD8B/JESD36 SCA75 613508/03/pp20 MDB105 sot762 footprint MNA423 74ALVC74BQ 74ALVC74D 74ALVC74PW DHVQFN14 TSSOP14 2SD92

    74AUP1G00GW

    Abstract: 74AUP1G00 74AUP1G00GF 74AUP1G00GM
    Text: 74AUP1G00 Low-power 2-input NAND gate Rev. 3 — 7 October 2010 Product data sheet 1. General description The 74AUP1G00 provides the single 2-input NAND function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall


    Original     		PDF 74AUP1G00 74AUP1G00 74AUP1G00GW 74AUP1G00GF 74AUP1G00GM

    74LVC2G86

    Abstract: 74LVC2G86DC 74LVC2G86DP 74LVC2G86GM 74LVC2G86GT
    Text: 74LVC2G86 Dual 2-input EXCLUSIVE-OR gate Rev. 8 — 19 October 2010 Product data sheet 1. General description The 74LVC2G86 provides a dual 2-input EXCLUSIVE-OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these


    Original     		PDF 74LVC2G86 74LVC2G86 74LVC2G86DC 74LVC2G86DP 74LVC2G86GM 74LVC2G86GT