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    ddr phy

    Abstract: master ATM controller ddr phy design
    Text: ispLever CORE TM UTOPIA Level 3 PHY Receive Interface User’s Guide October 2003 ipug21_01 Lattice Semiconductor UTOPIA Level 3 PHY Receive Interface Introduction The UTOPIA Level 3 PHY Receive core, UTOP3-PHYR, is one of four UTOPIA Level 3 cores available from Lattice.


    Original
    ipug21 af-phy-0136 1-800-LATTICE ddr phy master ATM controller ddr phy design PDF