HY62UF16201A-I
Abstract: HY62UF16201A
Text: HY62UF16201A Series 128Kx16bit full CMOS SRAM Document Title 128K x16 bit 3.0V Super Low Power Full CMOS Slow SRAM Revision History Revision No History Draft Date Remark 05 Divide output load into two factors - tCLZ,tOLZ,tBLZ,tCHZ,tOHZ,tBHZ,tWHZ,tOW - Others
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HY62UF16201A
128Kx16bit
HYUF621Ac
100ns
HY62UF16201A-I
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HY62UF16201A
Abstract: HY62UF16201A-I HY62UF16201AF HYUF621 REV08
Text: HY62UF16201A Series 128Kx16bit full CMOS SRAM Document Title 128K x16 bit 3.0V Super Low Power Full CMOS Slow SRAM Revision History Revision No 05 06 07 08 History Draft Date Remark Divide output load into two factors Dec.10. 2000 Final - tCLZ,tOLZ,tBLZ,tCHZ,tOHZ,tBHZ,tWHZ,tOW
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Original
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PDF
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HY62UF16201A
128Kx16bit
HY62UF16201AF1)
HY62UF16201AF)
HYUF621Ac
100ns
HY62UF16201A-I
HY62UF16201AF
HYUF621
REV08
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kor 2001
Abstract: MARKING HYNIX Origin Country HYNIX Origin Country
Text: HY62UF16201A Series 128Kx16bit full CMOS SRAM Document Title 128K x16 bit 3.0V Super Low Power Full CMOS Slow SRAM Revision History Revision No 05 06 07 History Draft Date Remark Divide output load into two factors Dec.10. 2000 Final - tCLZ,tOLZ,tBLZ,tCHZ,tOHZ,tBHZ,tWHZ,tOW
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Original
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PDF
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HY62UF16201A
128Kx16bit
HY62UF16201AF1)
HY62UF16201AF)
HYUF621Ac
100ns
kor 2001
MARKING HYNIX Origin Country
HYNIX Origin Country
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HYUF621
Abstract: No abstract text available
Text: H Y 6 2U F 1 620 1A S eries 128K X 16 b it fu ll CMOS SRAM DESCRIPTION FEATURES The HY62UF16201A is a high speed, super low power and 2Mbit full CMOS SRAM organized as 131,072 words by 16bits. The HY62UF16201A uses high performance full CMOS process technology and is designed for high speed and
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OCR Scan
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PDF
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HY62UF16201A
16bits.
48-FBGA
16bit
HYUF621AC
100ns
HYUF621
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