HY67V18100C Search Results

Contextual Info: •HYUNDAI H Y 6 7 V 1 8 1 0 0 /1 0 1 64K X 18 Bit SYNCHRONOUS CMOS SRAM PRELIMINARY DESCRIPTION This device integrates high-speed 64K x18 SRAM core, address registers, data input registers, a 2-bit burst ad­ dress counter and pipelined output. All synchronous inputs pass through registers controlled by a positiveedge triggered clock K .

Contextual Info: -HYUNDAI HY67V18100/101 64K X 18 Bit SYNCHRONOUS CMOS SRAM PRELIMINARY DESCRIPTION This device integrates high-speed 64K x18 SRAM core, address registers, data input registers, a 2-bit burst ad­ dress counter and pipelined output. All synchronous inputs pass through registers controlled by a positiveedge triggered clock K .

HY628400LLG

Abstract: HY628400LG-I HY628400LLP 8K*8 sram 52-PIN
Contextual Info: •HYU N DAI QUICK REFERENCE SRAM ORGANIZATION 64K bit 8Kx8 256K bit (32Kx8) 6 PART NUMBER SPEED(ns) FEATURES HY6264AP HY6264ALP HY6264ALLP HY6264AJ HY6264ALJ HY6264ALLJ 70/85/100/120 70/85/100/120 70/85/100/120 70/85/100/120 70/85/100/120 70/85/100/120