HY5S56E Search Results
HY5S56E Datasheets Context Search
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Contextual Info: 256MBit SDRAMs based on 4M x 4Bank x16 I/O Document Title 4Bank x 4M x 16bits Synchronous DRAM Revision History Revision No. History Draft Date Remark 0.1 Initial Draft Nov. 2004 Preliminary 0.2 Added Speed Product for 133MHz CL3 Jan. 2005 Preliminary This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for |
Original |
256MBit 16bits 133MHz 11Preliminary 16Mx16bit) HY5S56E 456bit A10/AP |