HY5MS7B2BL Search Results
HY5MS7B2BL Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
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Contextual Info: 512Mbit MOBILE DDR SDRAM based on 4M x 4Bank x32 I/O Document Title 512MBit 4Bank x 4M x 32bits MOBILE DDR SDRAM Revision History Revision No. History Draft Date Remark 0.1 - Initial Draft Sep.2006 Preliminary 0.2 - Added SRR function and timing diagram |
Original |
512Mbit 512MBit 32bits) LPDDR333 32bit) | |
H5TQ2G63BFR-H9C
Abstract: H5TQ1G83BFR-H9C H26M42001EFR H5RS1H23MFR h27u1g8f2b H27U1G8F2 H27UBG8T2A H27UBG8T H5MS2G22MFR-J3M H26M54001BKR
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Original |
256Mx4 H5TQ1G43BFR-H9C 78ball) H5TQ1G43TFR-H9C H5TQ1G43BFR-G7C H5TQ1G43TFR-G7C H5TQ1G83BFR-H9C H5TQ2G63BFR-H9C H5TQ1G83BFR-H9C H26M42001EFR H5RS1H23MFR h27u1g8f2b H27U1G8F2 H27UBG8T2A H27UBG8T H5MS2G22MFR-J3M H26M54001BKR | |
HY5MS7B2BL
Abstract: HY5MS7B2BLFP
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Original |
512MBit 512MBit 32bits) 16Mx32bit) 11Preliminary HY5MS7B2BL HY5MS7B2BLFP | |
Contextual Info: 512Mbit MOBILE DDR SDRAM based on 4M x 4Bank x32 I/ Document Title 512MBit 4Bank x 4M x 32bits MOBILE DDR SDRAM Revision History Revision No. History Draft Date Remark 0.1 - Initial Draft Sep.2006 Preliminary 0.2 - Added SRR function and timing diagram Jan.2007 |
Original |
512Mbit 512MBit 32bits) LPDDR333 32bit) |