HD74HC Search Results

Hitachi DSA0095

Abstract: DP-14 FP-14DA FP-14DN HD74HC30 TTP-14D
Contextual Info: HD74HC30 8-input NAND Gate ADE-205-416 Z 1st. Edition Sep. 2000 Features • • • • • High Speed Operation: tpd = 11 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max

Contextual Info: HD74HCT640 Octal Bus Transceivers with inverted 3-state outputs Octal Bus Transceivers (with 3-state outputs) REJ03D0672–0300 (Previous ADE-205-562A) Rev.3.00 Mar 30, 2006 Description The HD74HCT640 has one active low enable input (G), and a direction control (DIR). When the DIR input is high,

Contextual Info: HD74HCT620, HD74HCT623 Octal Bus Transceivers with inverted 3-state outputs Octal Bus Transceivers (with 3-state outputs) REJ03D0671–0200 (Previous ADE-205-561) Rev.2.00 Mar 30, 2006 Description This octal bus transceiver is designed for asynchronous two-way communication between data buses. The control

HD74HC00

Abstract: Hitachi DSA0095 DP-14 FP-14DA FP-14DN TTP-14D
Contextual Info: HD74HC00 Quad. 2-input NAND Gates ADE-205-403 Z 1st. Edition Sep. 2000 Features • • • • • High Speed Operation: tpd = 8.5 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max

Hitachi DSA0095

Abstract: DP-14 FP-14DA FP-14DN HD74HCU04A TTP-14D
Contextual Info: HD74HCU04A Hex Inverters ADE-205-288 Z 1st. Edition Jun. 1999 Description The HD74HCU04A has six inverters in a 14 pin package. Y = A Features • VCC = 4.5 to 5.5 V operation • Input terminal has protection diode Function Table Input A Output Y H L L

HD74HC05

Abstract: Hitachi DSA0095 DP-14 FP-14DA FP-14DN TTP-14D
Contextual Info: HD74HC05 Hex Inverters with Open Drain Outputs ADE-205-407 (Z) 1st. Edition Sep. 2000 Features • • • • • High Speed Operation: tpd = 8 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max

Contextual Info: HITACHI/ LO GIC/A R R A Y S/ M E M TE HD74HC194 DË J 4 4 ^ 2 0 3 001044 3 5 J ~ 92D 1 0 4 4 3 # 4-bit Bidirectional Universal Shift Register This bidirectional sh ift register is designed to incorporate P IN A R R A N G M E N T v irtu a lly all o f the features a system designer may w ant in

Contextual Info: HITACHI/ L O G I C / A R RA YS /M EM T2 , _ . D E I 4MtihSD3 001D37S 0 | ~ ~ 92D HD74HC123A # Dual Retriggerable Monostable Multivibrators with Clear This multivibrator features both a negative. A, and a positive, • PIN ARRANGEMENT B, transition triggered input, either of which can be used as

Contextual Info: HITACHI/ LOGIC/ARRAYS/MEM Ì2 dÊ J 44^303 0D1D44L. A | - HD74HC195 92D 10446 # 4-bit Parallel-Access Shift Register This shift register feetures parallel inputs, parallel outputs, J-K serial inputs, S hift/L oad control input, and a direct | D T- Hb -O l-ß S

Contextual Info: H I T A C H I / LOGIC/ARRAYS/flEH ^5 4 4 ^ 5 0 3 0010b44 1 92D HD 74H C T240 # 10644 D ]~'SZ-<>7 Octal B u ffers/Line D rivers/L ine Receivers with inverted 3-state outputs PIN ARRANGEMENT The HD74HCT240 is an inverting buffer and has two active low enables (1G and 2G). Each enable independently con­

Contextual Info: HITACHI/ LOGIC/ARRAYS/MEM HD74HCT137 TB DE 4 4 ^ 2 0 3 # 3-to-8-line Decoder/Dem ultiplexer with Address Latch | PIN ARRANGEMENT r-J-a T - , T ¡ ] Vcc B[T - B c^ - C Yi u jy. GL Yi ÏÏ]V i G L^ - A Yfl - C¡ Yi ¡ 2] Yi G i^ - Gi

Contextual Info: Ï Ë J 4 4 cit,2D3 G G 1 D 3 S 7 1 J H I T A C H I / L O G I C / A R R A Y S / N E M "il 92D HD74HC91 üT-ïé-ûf-O 10357 • 8 - bit Shift Register This serial-in, serial-out, 8-bit shift register is composed o f eight R-S master-slave flip-flo ps, inpu t gating, and a clock

Contextual Info: H I T A C H I / L O G I C / A R R A Y S / M E M ^2 D Ë J 4 MTticüOB OQlQSfl? 4 D T "H611 92D 10587 HD74HC678 16-bit Address Comparator The H D 7 4 H C 6 7 8 address comparator simplifies addressing of | P IN A R R A N G E M E N T m em ory boards and/or other peripheral devices. The four P

Contextual Info: "HITACHI/ L O G I C / A R RA YS /M En TS D E I 4 4 ^ 5 0 3 DD Id 3 Mb 4 | .9 2 D HD74HC76 • 10346 D T ~ Ÿ é ~ â 7 -û 7 Dual J-K Flip-Flops with Preset and Clear • PIN ARRANGEMENT Each flip -flo p has independent J, K , preset, clear, and clock

Contextual Info: HITACHI/ LOGI C / A R R A Y S/ M E M la HD74HC4060 D Ë J *44^203 O O l D b m 92D I VT-V5-2.3-n 10 61 4 # 14-stage Binary Counter The HD74HC4060 is a 14 stage counter, this device increments on the falling edge negative transition of the input | I PIN ARRANGEMENT

Contextual Info: HITACHI/ LOeiC/ARRAYS/riEM TE HD74HC323 DË| ^ ^ 5 0 3 Oq i o m ö T 4 # 8-bit Universal Shift/Storage Register with 3-state Outputs This eight-bit universal register features m ultiplexed I/O ports to achieve fu ll eight b it data handling in a single 20*pin

Contextual Info: HITACH I/ LOGIC/ARRAYS/MEfl ì n j 44Tb2D3 00104L.7 5 J~~ -> HD74HC253 92D 10467 D # Dual 4-to-l-line Data Selectors/Multiplexers with 3-state outputs r * b * 7 " X l - 5 1 T he large ou tp u t drive a n d 3-state features o f this device P IN A R R A N G E M E N T

Contextual Info: HITACHI/ L O G I C / A R R A Y S / M E N 'ÎH D eJ 44^203 DOlObbb Q 10666 d 7 "-S 2 -3 Ì 92D HD74HCT640,HD74HCT643 Both the HD74HCT640 and the HD74HCT643 have one active low enable Input G , and a direction control (D IR ). When the DIR Input li high, data flow i from the A Inputi

Contextual Info: HITACHI/ LOGIC/ARRAYS/HEfl TS D E | l44^13203 D O l O M h T ; HD74HC257 92D T 10469 D # Quad.2-to- 1-line Data Selectors/Multiplexers with noninverted 3-state outputs) -T -lcH-'LlSl PIN ARRANGEMENT The large output drive capability coupled with the 3-state

Contextual Info: H I T A C H I ^ L O G I C / A R R A Y S / M E M TS D E j 44Tb2D3 DDlGblO 92D HD74HC4040 # 10610 T - H 5 ~ 3 3 - n 12-stage Binary Counter The HD74HC4040 is a 12 stage counter. This device is incre- | D PIN ARRANGEMENT merited on the falling edge negative transition} of the input

Contextual Info: HITACHI/ L O G IC /A RRAYS/ NEN ^2 D E I 4 4 ^ 5 0 3 GD1D413 4 J ~ 92D HD74HC165 # 10413 Parallel-load 8-bit Shift Register This 8-bit serial shift register shifts data fro m Q A to Q h T-46-09-05 PIN ARRANGEMENT when clocked. Parallel inputs to each stage are enabled by a

Contextual Info: HITACHI/ LOGIC/ARRAYS/MEM TS 44^203 00104^ 3 HD74HC356 92D 7 | 10499 D 18-to-l-line Data Selector/M ultiplexer/Register with 3-state outputs) - T - b - 7 - 2 1 - £ 7 This data selectors/multiplexers contain full on-chip binary

Contextual Info: HITACHI/ L O G I C / A R R A Y S / M E M T2 DËJ 4 4 ^ 2 0 3 GülD4ñb I 9 2D HD74HC299 # 8-bit Universal Shift/Storage Register The H D 7 4 H C 2 9 9 features multiplexed Inputs/outputs to achieve full 8-bit data .handling in a single 20-pin package. | V .T -% -0 ? -0 S

Contextual Info: H IT A C H I/ L O G I C / A R R A Y S /flEd ^2 D E I 44TbE03 D D lD t4 2 92D HD74HCT238 • fi 10642 3-to-8-line Decoder/D em ultiplexer The HD74HCT238 has 3 binary select inputs A, B, and C . if the device is enabled these inputs determined which one of