HC NOT GATE Search Results

pelco

Abstract: ACARD pelco-d ADR7604S "media player software"
Contextual Info: 4CH H.264 Standalone DVR ADR7604SC/HC User Manual Version 1.0 Statement The information of the product in this manual is subject to change without prior notice and does not represent a commitment on the part of vendor, who assumes no liability or responsibility for any errors that may appear in this manual.

AN9607

Abstract: HC5517 Adjustable Power Supply Schematic Diagram 40vdc
Contextual Info: NS ESIG D W TM R NE UCT D FO E PROD E D MEN ITUT 5186 COM SUBST 85, HC5 E R 551 NOT SSIBLE ,Data 1 HC Sheet 7 PO 1 5 HC5 3 REN Ringing SLIC For ISDN Modem/TA and WLL 4147.3 • Sinusoidal Ringing Capability • DI Process Provides Substrate Latch Up Immunity when

nec sgp

Abstract: A13286EJ1V0UM00
Contextual Info: Preliminary User’s Manual USB Host Controller µPD9210FGC-7EA Document No. A13286EJ1V0UM00 1st edition Date Published July 1998 N CP(N) 1998 Printed in Japan [MEMO] 2 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

Contextual Info: ASSESS? CD74HC367, CD74HCT367, CD74HC368, CD74HCT368 High Speed CMOS Logic Hex Buffer/Line Driver, Three-State Non-Inverting and Inverting November 1997 Features Description • Buffered Inputs The Harris CD74HC367, CD74HCT367, CD74HC368, and CD74HCT368 silicon gate CMOS three-state buffers are gen­

NCP4115

Abstract: NCP4100 200v npn 3a d2pak NCP1450 Bipolar Power Transistor Data 400V igbt dc to dc buck converter 12V to 300V dc dc converter step-up NCP1650 NCP1204 DL135
Contextual Info: Rev. 10, 3Q02 SGD503/D POWER MANAGEMENT SOLUTIONS ANALOG PRODUCTS DC/DC: Multiphase Controllers DEVICE NCP5316 NCP5332A POWER MANAGEMENT SOLUTIONS ANALOG cont. GATE DRIVE External On-chip COMPLIANCE VRM 10 VRM 9.0 PACKAGE AVAILABILITY QFN-44 7*7 4Q02 SO-28W

74HCT

Abstract: 74LS CD74HC03 CD74HC03E CD74HC03M CD74HCT03 CD74HCT03E CD74HCT03M CT03
Contextual Info: [ /Title CD74H C03, CD74H CT03 /Subject (High Speed CMOS Logic Quad 2Input CD74HC03, CD74HCT03 Data sheet acquired from Harris Semiconductor SCHS126 High Speed CMOS Logic Quad 2-Input NAND Gate with Open Drain February 1998 Features Description • Buffered Inputs

74HCT03

Abstract: HCT400
Contextual Info: [ /Title CD74H C03, CD74H CT03 /Subject (High Speed CMOS Logic Quad 2Input CD54/74HC03, CD54/74HCT03 Data sheet acquired from Harris Semiconductor SCHS126A High Speed CMOS Logic Quad 2-Input NAND Gate with Open Drain February 1998 - Revised May 2000 Features

Gates

Abstract: 74HC03M96 CD54HC03 CD54HC03F3A CD54HCT03 CD54HCT03F3A CD74HC03 CD74HCT03 CT03
Contextual Info: [ /Title CD74H C03, CD74H CT03 /Subject (High Speed CMOS Logic Quad 2Input CD54HC03, CD74HC03, CD54HCT03, CD74HCT03 Data sheet acquired from Harris Semiconductor SCHS126D High-Speed CMOS Logic Quad 2-Input NAND Gate with Open Drain February 1998 - Revised September 2003

CD54HC03

Abstract: CD54HC03F3A CD54HCT03 CD54HCT03F3A CD74HC03 CD74HCT03 CT03
Contextual Info: [ /Title CD74H C03, CD74H CT03 /Subject (High Speed CMOS Logic Quad 2Input CD54HC03, CD74HC03, CD54HCT03, CD74HCT03 Data sheet acquired from Harris Semiconductor SCHS126C High-Speed CMOS Logic Quad 2-Input NAND Gate with Open Drain February 1998 - Revised May 2003

Contextual Info: [ /Title CD74H C03, CD74H CT03 /Subject (High Speed CMOS Logic Quad 2Input CD54/74HC03, CD54/74HCT03 Data sheet acquired from Harris Semiconductor SCHS126B High Speed CMOS Logic Quad 2-Input NAND Gate with Open Drain February 1998 - Revised December 2002

CD54HC03

Abstract: CD54HC03F3A CD54HCT03 CD54HCT03F3A CD74HC03 CD74HCT03 CT03 SCHS126D
Contextual Info: [ /Title CD74H C03, CD74H CT03 /Subject (High Speed CMOS Logic Quad 2Input CD54HC03, CD74HC03, CD54HCT03, CD74HCT03 Data sheet acquired from Harris Semiconductor SCHS126D High-Speed CMOS Logic Quad 2-Input NAND Gate with Open Drain February 1998 - Revised September 2003

CD54HC03

Abstract: CD54HC03F3A CD54HCT03 CD54HCT03F3A CD74HC03 CD74HCT03 CT03
Contextual Info: [ /Title CD74H C03, CD74H CT03 /Subject (High Speed CMOS Logic Quad 2Input CD54HC03, CD74HC03, CD54HCT03, CD74HCT03 Data sheet acquired from Harris Semiconductor SCHS126D High-Speed CMOS Logic Quad 2-Input NAND Gate with Open Drain February 1998 - Revised September 2003

4000 series CMOS Logic levels 18 - 24v

Abstract: PVAPOX
Contextual Info: GENERAL AND APPLICATION INFORMATION INTRODUCING HS-C2 MOS High Speed The rapid advances recently m ade in silicon-gate CM OS technology have lead to the introduction of a logic fam ily that sets new and much higher stand­ ards of performance. This fam ily called HS-C2MOS*, exhibits a greatly

Contextual Info: [ /Title CD74H C03, CD74H CT03 /Subject (High Speed CMOS Logic Quad 2Input CD54/74HC03, CD54/74HCT03 Data sheet acquired from Harris Semiconductor SCHS126A High Speed CMOS Logic Quad 2-Input NAND Gate with Open Drain February 1998 - Revised May 2000 Features

Contextual Info: [ /Title CD74H C03, CD74H CT03 /Subject (High Speed CMOS Logic Quad 2Input CD54HC03, CD74HC03, CD54HCT03, CD74HCT03 Data sheet acquired from Harris Semiconductor SCHS126D High-Speed CMOS Logic Quad 2-Input NAND Gate with Open Drain February 1998 - Revised September 2003

CD74HC00

Abstract: 74HCT 74LS CD54 CD54HC00 CD54HCT00 CD74HCT00 HC00 HCT00
Contextual Info: [ /Title CD54 HC00, CD54 HCT00 , CD74 HC00, CD74 HCT00 /Sub- CD54HC00, CD54HCT00, CD74HC00, CD74HCT00 Data sheet acquired from Harris Semiconductor SCHS116 High Speed CMOS Logic Quad 2-Input NAND Gate January 1998 Features Description • Buffered Inputs

Contextual Info: [ /Title CD74H C03, CD74H CT03 /Subject (High Speed CMOS Logic Quad 2Input CD54HC03, CD74HC03, CD54HCT03, CD74HCT03 Data sheet acquired from Harris Semiconductor SCHS126D High-Speed CMOS Logic Quad 2-Input NAND Gate with Open Drain February 1998 - Revised September 2003

Contextual Info: [ /Title CD74H C03, CD74H CT03 /Subject (High Speed CMOS Logic Quad 2Input CD54HC03, CD74HC03, CD54HCT03, CD74HCT03 Data sheet acquired from Harris Semiconductor SCHS126D High-Speed CMOS Logic Quad 2-Input NAND Gate with Open Drain February 1998 - Revised September 2003

Contextual Info: CD74HC03, CD74HCT03 S E M I C O N D U C T O R High Speed CMOS Logic Quad 2-Input NAND Gate with Open Drain February 1998 Features Description • Buffered Inputs The Harris CD74HC03 and CD74HCT03 logic gates utilize silicon gate CMOS technology to achieve operating speeds

Contextual Info: CD54HCT32, CD74HC32, CD74HCT32 HARRIS S E M I C O N D U C T O R High Speed CMOS Logic Quad 2-Input OR Gate August 1997 Features Description • Typical Propagation Delay: 7ns at Vcc = 5V, C L = 15pF, Ta = 25°C The Harris CD74HC32, CD74HCT32 contain four 2-input OR

CD74HC7266

Abstract: CD74HC7266E CD74HC7266M HC7266 TTL226
Contextual Info: [ /Title CD74H C7266 /Subject (High Speed CMOS Logic Quad 2Input EXCLUSIVE CD74HC7266 Data sheet acquired from Harris Semiconductor SCHS219 High Speed CMOS Logic Quad 2-Input EXCLUSIVE NOR Gate August 1997 Features Description • Four Independent EXCLUSIVE NOR Gates

74HCT

Abstract: 74LS CD74HC20 CD74HC20E CD74HC20M CD74HCT20 CD74HCT20E CD74HCT20M
Contextual Info: [ /Title CD74H C20, CD74H CT20 /Subject (High Speed CMOS Logic Dual 4Input CD74HC20, CD74HCT20 Data sheet acquired from Harris Semiconductor SCHS130 High Speed CMOS Logic Dual 4-Input NAND Gate August 1997 Features Description • Buffered Inputs The Harris CD74HC20, CD74HCT20, logic gates utilize

74LS logic gates

Abstract: CD74HC32 CD54 CD54HC32F3A CD54HCT32 CD54HCT32F3A CD74HCT32 HCT32 74HCT 74LS
Contextual Info: [ /Title CD54 HCT32 , CD74 HC32, CD74 HCT32 /Subject (High CD54HCT32, CD74HC32, CD74HCT32 Data sheet acquired from Harris Semiconductor SCHS274 High Speed CMOS Logic Quad 2-Input OR Gate September 1997 Features Description • Typical Propagation Delay: 7ns at VCC = 5V,

CD54HC7266

Abstract: CD54HC7266F3A CD74HC7266 CD74HC7266E CD74HC7266M CD74HC7266MT HC7266 TTL226
Contextual Info: [ /Title CD74H C7266 /Subject (High Speed CMOS Logic Quad 2Input EXCLUSIVE CD54HC7266, CD74HC7266 Data sheet acquired from Harris Semiconductor SCHS219D High-Speed CMOS Logic Quad 2-Input EXCLUSIVE NOR Gate August 1997 - Revised September 2003 Features Description