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    GATES Search Results

    GATES Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    7UL1G32NX Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), 2-Input/OR, XSON6, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    7UL1G86NX Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), 2-Input/Exclusive-OR, XSON6, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    7UL1G00NX Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), 2-Input/NAND, XSON6, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    7UL1G08NX Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), 2-Input/AND, XSON6, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    7UL1G02NX Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), 2-Input/NOR, XSON6, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
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    onsemi STR-LOGIC-GATES-EVK

    EVAL BOARD FOR NL7SZ58 NL7SZ97
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    DFI-ITOX SB630-GATES

    CUSTOM Q87 ATX MOTHERBOARD FOR GATESAIR - Bulk (Alt: SB630-GATES)
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    ADLINK Technology Inc Seagate, ST2000LM015

    Hard Disk Drives - HDD HDD, SATA, 6Gb/s 2.5" 7mm, 2TB 5400RPM Heads:4, Disk:2 Cache buffer:128MB
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    Mouser Electronics Seagate, ST2000LM015 1
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    ADLINK Technology Inc SEAGATE ST1000LM049

    Hard Disk Drives - HDD HDD, SATA, 6Gb/s, 2.5" ,7mm, 1TB, 7200RPM, Heads:2, Disk:1, Cache buffer:128MB, OP Temp:0-60
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    Mouser Electronics SEAGATE ST1000LM049
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    ADLINK Technology Inc SEAGATE ST500LM030

    Hard Disk Drives - HDD HDD, SATA, 6Gb/s, 2.5" ,7mm, 500GB, 5400RPM, Heads:2, Disk:1, Cache buffer:128MB, OP Temp:0-60
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    Mouser Electronics SEAGATE ST500LM030
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    GATES Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    Untitled

    Abstract: No abstract text available
    Text: TOSHIBA TC4030BP/BF/BFN TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC Tran^riRP Tran^fiRF Trzin^nRFM • ^ w » . g ■ ^ w » . f ■ 'w ■■ - - Note The JEDEC SOP (FN) is not available in TC4030B QUAD EXCLUSIVE - OR GATE Japan. TC4030B contains four circuits of exclusive OR gates. Since


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    TC4030BP/BF/BFN TC4030B 14PIN DIP14-P-300-2 14PIN 200mil OP14-P-300-1 PDF

    Untitled

    Abstract: No abstract text available
    Text: SN5409, SN54LS09, SN54S09, SN7409, SN74LS09, SN74S09 QUADRUPLE 2-INPUT POSITIVE-AND GATES WITH OPEN-COLLECTOR OUTPUTS DECEMBER 1 9 8 3 -R E V IS E D M A R C H 1 9 8 8 Package Options Include Plastic "Sm all Outline" P ackages, Ceram ic Chip Carriers and Flat P ackages, and Plastic and Ceram ic


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    SN5409, SN54LS09, SN54S09, SN7409, SN74LS09, SN74S09 PDF

    7408, 7404, 7486, 7432

    Abstract: RF400U functional diagram of 7400 and cd 4011 ls 7404 180 nm CMOS standard cell library TEXAS INSTRUMENTS 74191 4BITS s273 buffer 74374 7408 CMOS cmos 7404
    Text: TGC100 Series CMOS Gate Arrays RELEASE 3.0, REVISED JANUARY 1990 • Twelve Arrays with up to 26K Available Gates • Fast Prototype Turnaround Time • Extensive Design Support - Design Libraries Compatible with Daisy, Valid, and Mentor CAE Systems - Tl Regional ASIC Design Centers


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    TGC100 20-mA Sink/12mA TDB10LJ 120LJ TDC11LJ TDN11LJ 100MHz 7408, 7404, 7486, 7432 RF400U functional diagram of 7400 and cd 4011 ls 7404 180 nm CMOS standard cell library TEXAS INSTRUMENTS 74191 4BITS s273 buffer 74374 7408 CMOS cmos 7404 PDF

    Untitled

    Abstract: No abstract text available
    Text: 54AC11032, 74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES TI0060— D2957, JULY 1987— REVISED MARCH 1990 54A C 11032 . . . J PACKAGE 74A C 11032 . . . D OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout TOP VIEW • Center-Pin V c c and GND Configurations to


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    54AC11032, 74AC11032 TI0060-- D2957, 500-mA 300-mil 54AC11032 PDF

    Untitled

    Abstract: No abstract text available
    Text: 54AC11021,74AC11021 DUAL 4-INPUT POSITIVE-AND GATES _ D2957. JULY 1987 - REVISED APRIL 1993 54AC11021 . . . J PACKAGE 74AC11021 . . . D OR N PACKAGE TOP VIEW * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations


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    54AC11021 74AC11021 D2957. 500-mA 300-mll PDF

    Untitled

    Abstract: No abstract text available
    Text: 54AC11002, 74AC11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES D2957, JUNE 1987 - REVISED APRIL 1993 54AC11002 . . . J PACKAGE 74AC11002 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin Vcc and GND Configuration Minimizes High-Speed Switching Noise


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    54AC11002, 74AC11002 D2957, 500-mA 300-mil 54AC11002 PDF

    IC SN74HC

    Abstract: SN74HCTOO SN74HC
    Text: SN54HCT00, SN74HCT00 QUADRUPLE 2-INPUT POSITIVE NANO GATES D 3 2 4 3 , NOVEMBER 1968 Inputs are TTL-Voftage Compatible S N 54H C T00 S N 74H C T00 Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil


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    SN54HCT00, SN74HCT00 300-mil 74Herating SN54HC SN74HC IC SN74HC SN74HCTOO PDF

    marking 3G

    Abstract: No abstract text available
    Text: TC4S01F TO SHIBA C MOS DIGITAL INTEGRATED C IR C U IT SILICO N M ONOLITHIC 2 INPUT NOR GATE Unit in mm + 0.2 23-0.3 The TC4S01F is 2-input positive logic NOR gates. + 0.2 Gate output w ith in v e rte r buffer im proves the 16 input-output ch arac te ristic s and if th e load


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    TC4S01F TC4S01F Ta-25 marking 3G PDF

    Untitled

    Abstract: No abstract text available
    Text: TOSHIBA TC4S11F TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC4S11F 2 INPUT N A N D GATE The TC4S11F is 2-input positive logic NAND gates. Gate output with inverter buffer improve the inputoutput characteristics and even if the load capacitance


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    TC4S11F TC4S11F PDF

    logic diagram of 7432

    Abstract: Texas Instruments TTL 7432
    Text: SN5432, SN 54LS32, SN54S32. SN7432, SN74LS32, SN74S32 QUADRUPLE 2-INPUT POSITIVE-OR GATES DECEMBER 1983-REVISED MARCH 1988 Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs • SN 5432. SN 54LS32, SN 54S 32 . . . J OR W PACKAGE


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    SN5432, 54LS32, SN54S32. SN7432, SN74LS32, SN74S32 1983-REVISED SN54LS32 logic diagram of 7432 Texas Instruments TTL 7432 PDF

    74ALS8003

    Abstract: No abstract text available
    Text: TYPES SN54ALS8003, SN74ALS8003 DUAL 2-INPUT POSITIVE-NAND GATES D 2 7 4 6 . JU LY 1 9 8 3 -R E V IS E D DECEMBER 1 9 8 3 • Package Options Include Both Plastic and Ceramic Chip Carriers in Addition to Plastic and Ceramic DIPs. S N 54A LS 8003 . . . JG PACKAGE


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    SN54ALS8003, SN74ALS8003 LS8003 74ALS8003 PDF

    Untitled

    Abstract: No abstract text available
    Text: SN54LS15, SN54S15, SN74LS15, SN74S15 TRIPLE 3 INPUT POSITIVE AND GATES WITH OPEN-COLLECTOR OUTPUTS A P R IL 1 9 8 5 — R E V IS E D M A R C H Package Options Include Plastic "Sm all Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic


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    SN54LS15, SN54S15, SN74LS15, SN74S15 PDF

    Untitled

    Abstract: No abstract text available
    Text: SN54F20, SN74F20 DUAL 4-INPUT POSITIVE-NAND GATES D2932, MARCH 1987-REVISED JANUARY 1989 • Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs S N 5 4 F 2 0 . . . J PACKAGE S N 7 4 F 2 0 . . . 0 OR N PACKAGE


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    SN54F20, SN74F20 D2932, 1987-REVISED 300-mil 54F20 SN54F20 PDF

    Untitled

    Abstract: No abstract text available
    Text: SN54HC132, SN74HC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS034B - DECEMBER 1982 - REVISED JANUARY 1996 • • • • • Operation From Very Slow Input Transitions Temperature-Compensated Threshold Levels High Noise Immunity Same Pinouts as ’HCOO


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    SN54HC132, SN74HC132 SCLS034B 300-mll SN54HC132 SN74HC132 PDF

    Untitled

    Abstract: No abstract text available
    Text: 54ACT11002,74ACT11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCAS003A - D2957, JUNE 1987 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-PIn V^c and GND Configurations Minimize High-Speed Switching Noise


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    54ACT11002 74ACT11002 SCAS003A D2957, 500-mA 300-mll PDF

    Untitled

    Abstract: No abstract text available
    Text: SN54ALS11A, SN54AS11, SN74ALS11A, SN74AS11 TRIPLE 3-INPUT POSITIVE-AND GATES SDAS009C - MARCH 1984 - REVISED DECEMBER 1994 • Package Options Include Plastic Small-Outline D Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs


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    SN54ALS11A, SN54AS11, SN74ALS11A, SN74AS11 SDAS009C 300-mil SN54AS11 SNS4ALS11 SN54AS11 PDF

    74as32

    Abstract: No abstract text available
    Text: SN54ALS32, SN54AS32, SN74ALS32, SN74AS32 QUADRUPLE 2-INPUT POSITIVE-OR GATES D 2 6 6 1 , A P R IL 1 9 8 2 - R E V I S E D M A Y 1 9 8 6 • Package Options Include Plastic "Sm all Outline" Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-m il


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    SN54ALS32, SN54AS32, SN74ALS32, SN74AS32 300-m 74as32 PDF

    Untitled

    Abstract: No abstract text available
    Text: TC4S71F TOSHIBA C MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 2 INPUT OR GATE Unit in nm The TC4S71F contains 2-input positive logic O R gates. + 0.2 1.6-5.1 Gate output with inverter buffer improves the input-output ch aracteristics and if the load


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    TC4S71F TC4S71F Ta-25 C/10sec. CL-50pF) PDF

    Untitled

    Abstract: No abstract text available
    Text: TC4S81F 2 INPUT AND GATE T he TC4S81F is 2 -in p u t p o s itiv e lo g ic A N D gates. G ate o u t p u t w ith in v e rte r b u ffe r im p ro v e th e in p u to u t p u t c h a ra cte ristics a n d even if th e lo a d ca p a citan ce increases, it can be s to p p e d th e ch a n g e o f p ro p a g a tio n


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    TC4S81F TC4S81F PDF

    64LS11

    Abstract: 74LS11M
    Text: SN54LS11, SN54S11, SN74LS11, SN74S11 TRIPLE 3 INPUT POSITIVE AND GATES APRIL 1 9 8 5 - R E V I S E D M A R C H 1 9B 8 • • Package Options Include Plastic "Sm all O utline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs


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    SN54LS11, SN54S11, SN74LS11, SN74S11 54LS11, SN74S11 64LS11 74LS11M PDF

    Untitled

    Abstract: No abstract text available
    Text: SN54HC03, SN74HC03 QUADRUPLE 2-INPUT POSITIVE-NAMD GATES WITH OPEN-DRAIN OUTPUTS _ Package Options Include Plastic Small-Outllne D and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mll DIPs


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    SN54HC03, SN74HC03 300-mll SN54HC03 SN74HC03 PDF

    Untitled

    Abstract: No abstract text available
    Text: SN54F30, SN74F30 8-INPUT POSITIVE-NANO GATES D2932, MARCH 1987-R E V ISE D JANUARY 1989 SN 54F30 . . . J PACKAG E SN 74F30 D OR N P A C K A G E Package Options Includa Plastic "Sm all Outline" Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mII


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    SN54F30, SN74F30 D2932, 1987-R 300-mII 54F30 74F30 SN54F30 PDF

    12-INPUT

    Abstract: No abstract text available
    Text: TYPES SN54S134, SN74S134 12-INPUT POSITIVE-NAND GATES WITH 3-STATE OUTPUTS R E V IS E D D E C E M B E R 1983 Package Options Include Both Plastic and Ceramic Chip Carriers in Addition to Plastic and Ceramic DIPs S N 5 4 S 1 3 4 . . . J OR W PACKAGE S N 7 4 S 1 3 4 . . . D , J OR N PACKA GE


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    SN54S134, SN74S134 12-INPUT PDF

    Untitled

    Abstract: No abstract text available
    Text: TC4085BP C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC4085BP DUAL 2-WIDE 2-INPUT AND-OR-INVERT GATE TC4085BP contains two circuits of AND-OR select gates and the outputs are inverted. The circuit consists of two 2 input AND gates and one NOR gate,


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    TC4085BP TC4085BP TC4081B, PDF