LMH6612QML
Abstract: 5962R0722701VZA SOIC-10 CQFP-128 DS90LV032QML LM117HQML LM723 LM723 application notes CQFP-48 5962R0722701
Text: Space Solutions Selection Guide national.com/space 2010 Vol. 1 Imaging Solutions Signal Path Solutions Amplifier Solutions Power Management Interface Solutions ELDRS-Free Products Power S/S Solar Array N&S Power Distribution Unit Core Power Pwr Bus #1 Pwr Bus #2
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Untitled
Abstract: No abstract text available
Text: NCN2411 4-Channel Differential 1:2 Mux/Demux Switch for PCI Express Gen2 The NCN2411 is a 4−Channel differential SPDT switch designed to route PCI Express Gen2 signals. When used in a PCI Express application, the switch can handle up to two PCIe lanes. Due to the
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NCN2411
WQFN42
NCN2411/D
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Untitled
Abstract: No abstract text available
Text: NCN2411 4-Channel Differential 1:2 Mux/Demux Switch for PCI Express Gen2 The NCN2411 is a 4−Channel differential SPDT switch designed to route PCI Express Gen2 signals. When used in a PCI Express application, the switch can handle up to two PCIe lanes. Due to the
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NCN2411
NCN2411
WQFN42
WQFN42
510AP
NCN2411/D
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Untitled
Abstract: No abstract text available
Text: NCN3411 4-Differential Channel 1:2 Mux/Demux Switch for PCI Express Gen3 The NCN3411 is a 4−Channel differential SPDT switch designed to route PCI Express Gen3 signals. When used in a PCI Express application, the switch can handle up to two PCIe lanes. Due to the
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NCN3411
WQFN42
NCN3411/D
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Untitled
Abstract: No abstract text available
Text: NCN3411 4-Differential Channel 1:2 Mux/Demux Switch for PCI Express Gen3 The NCN3411 is a 4−Channel differential SPDT switch designed to route PCI Express Gen3 signals. When used in a PCI Express application, the switch can handle up to two PCIe lanes. Due to the
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NCN3411
NCN3411
WQFN42
WQFN42
NCN3411/D
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Arrayed Waveguide Grating
Abstract: 25 ghz channel spacing arrayed waveguide grating 7349 50 ghz Arrayed Waveguide Grating AWG16SN AWG40SN GR-1209 Low PDL grating ArrAyed waveguide
Text: http://samsungfiberoptics.com Arrayed Waveguide Grating Mux/DeMux Arrayed Waveguide Grating Mux/DeMux Temperature Controller Embeded Type (Standard Type) Excellence in Samsung’s PLC products is first found in the waveguide fabrication methodology using low loss Flame Hydrolysis Deposition as technology platform with
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1-877-ssoptic
Arrayed Waveguide Grating
25 ghz channel spacing arrayed waveguide grating
7349
50 ghz Arrayed Waveguide Grating
AWG16SN
AWG40SN
GR-1209
Low PDL grating
ArrAyed waveguide
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Si5110-BC
Abstract: Si5100 Si5100-BC Si5110 Si5364 oc48 transponder
Text: Si5110/5100 SiPHY OC-48/STM-16 SONET/SDH TRANSCEIVER FEATURES • Integrated limiting amplifier, CDR, CMU, and MUX/DEMUX • Data rates supported: OC-48/STM-16, 2.7 Gbps FEC • DSPLL based clock multiplier unit with selectable loop filter bandwidths 12 kHz,
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Si5110/5100
OC-48/STM-16
OC-48/STM-16,
Si5110
Si5100
Si5364
Si5110-BC
Si5100-BC
oc48 transponder
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Si5100
Abstract: Si5100-BC Si5110 Si5110-BC Si5364
Text: Si5100/5110 SiPHY OC-48/STM-16 SONET/SDH TRANSCEIVER FEATURES • Integrated limiting amplifier, CDR, CMU, and MUX/DEMUX • Data rates supported: OC-48/STM-16, 2.7 Gbps FEC • DSPLL™ based clock multiplier unit with selectable loop filter bandwidths 6 kHz
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Si5100/5110
OC-48/STM-16
OC-48/STM-16,
Si5100
Si5110
Si5100-BC
Si5110-BC
Si5364
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Si5530
Abstract: Si5530-BC Si5540 Si5540-BC Si5600 Si5600-BC Si5364 Signal Path Designer
Text: Si5600 SiPHY OC-192/STM-64 SONET/SDH TRANSCEIVER FEATURES • Integrated limiting amplifier, CDR, CMU, and MUX/DEMUX • Data rates supported: OC-192/STM-64, 10 GbE, 10.7 Gbps FEC • Low power operation 1.2 W typ • DSPLL™ based clock multiplier unit with
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Si5600
OC-192/STM-64
OC-192/STM-64,
Si5600
Si5600;
Si5600-BC
Si5530-BC
Si5540-BC
Si5530
Si5540
Si5364
Signal Path Designer
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Si5020
Abstract: Si5100 Si5110 OC-48 STM-16 OC-48 Clock and data recovery
Text: OC-48 Optical Networking Solutions HIGH PERFORMANCE PHYSICAL LAYER ICS KEY PRODUCTS Si5100/10 Transceivers • Data rates supported: OC-48/STM-16 and 2.7 Gbps FEC • Integrated limiting amplifier, CDR, CMU and Mux/Demux • DSPLL-based CMU with selectable loop
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OC-48
Si5100/10
OC-48/STM-16
Si5110)
Si5100)
Si5022/23
OC-3/12/48,
STM-1/4/16,
Si5110
Si5100
Si5020
Si5100
Si5110
STM-16
OC-48 Clock and data recovery
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MAX9150
Abstract: MAX9152 MAX9205 MAX9206
Text: Maxim > App Notes > BASESTATIONS / WIRELESS INFRASTRUCTURE INTERFACE CIRCUITS HIGH-SPEED INTERCONNECT Keywords: LVDS, low voltage, differential signaling, signalling, lvds, EIA/TIA-644, 3G, signal distribution, clock distribution, W-CDMA, EDGE, CDMA2000, basestations
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EIA/TIA-644,
CDMA2000,
EIA/TIA-644
CDMA2000
com/an1058
MAX9150:
MAX9152:
MAX9205:
MAX9206:
MAX9150
MAX9152
MAX9205
MAX9206
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Finisar CA 94089
Abstract: 100G TOSA TOSA finisar TOSA DWDM finisar 100g DWDM 50 GHz Demux DWDM COLOR TOSA
Text: Passive Optical Products PRODUCT GUIDE With over two decades of industry experience, Finisar is recognized as a global optics technology leader and the world’s largest supplier of optical communication components. Finisar takes pride in its reputation for exceptional customer
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in389
Finisar CA 94089
100G TOSA
TOSA finisar
TOSA DWDM
finisar 100g
DWDM 50 GHz Demux
DWDM COLOR
TOSA
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AN642
Abstract: APP642 MAX104 MAX105 MAX106 MAX107 MAX108 circuitry interleaving introduction of demux
Text: Maxim > App Notes > A/D and D/A Conversion/Sampling Circuits High-Speed Signal Processing Keywords: ultra fast, 8-bit, high-speed, data converters, analogue to digital, analog to digital, converter, ADCs, high dynamic, AC performance, GHz input bandwidth, interleaving, synchronizing, synchronized, demultiplexer, demux, reset,
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MAX104/6/8
MAX105:
MAX106:
MAX107:
MAX108:
com/an642
AN642,
APP642,
Appnote642,
AN642
APP642
MAX104
MAX105
MAX106
MAX107
MAX108
circuitry interleaving
introduction of demux
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Untitled
Abstract: No abstract text available
Text: EV10AS180A Low Power L-Band 10-bit 1.5 GSps ADC ANALOG to DIGITAL CONVERTER Datasheet Main Features • • • • • • • • • • • • • Single Core ADC Architecture with 10-bit Resolution Integrating a Selectable 1:1/2/4 DEMUX 1.5 GSps Guaranteed Conversion Rate
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EV10AS180A
10-bit
1096Câ
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LA0-RD37
Abstract: No abstract text available
Text: PRELIMINARY DS3131 BoSS Bit SynchronouS HDLC Controller www.maxim-ic.com FEATURES § § § § § § 40 timing independent bit synchronous ports 40Rx and 40Tx coupled with 40 independent Bidirectional HDLC channels Each port can operate up to 52 Mbps 132Mbps full-duplex throughput
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DS3131
132Mbps
25MHz
33MHz
32-bit
DS3134
DS3131
DS3131.
LA0-RD37
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TP31C
Abstract: PCI Backplane DS3131 DS3134 TC10 TC12 TD39 811af 32 bit pci backplane LD0-TC28
Text: DS3131 BoSS Bit SynchronouS HDLC Controller www.dalsemi.com FEATURES • • • • • • • • • • • 40 timing independent bit synchronous ports 40Rx & 40Tx coupled with 40 independent Bi-directional HDLC channels Each port can operate up to 52 Mbps
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DS3131
32-bit
DS3131
DS3131.
TP31C
PCI Backplane
DS3134
TC10
TC12
TD39
811af
32 bit pci backplane
LD0-TC28
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TP31C
Abstract: LA0-RD37 RC20
Text: PRELIMINARY DS3131 BoSS Bit SynchronouS HDLC Controller www.maxim-ic.com FEATURES § § § § § § 40 timing independent bit synchronous ports 40Rx and 40Tx coupled with 40 independent Bidirectional HDLC channels Each port can operate up to 52 Mbps 132Mbps full-duplex throughput
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DS3131
132Mbps
25MHz
33MHz
32-bit
DS3134
DS3131
DS3131.
TP31C
LA0-RD37
RC20
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AN1058
Abstract: MAX9150 MAX9152 MAX9205 MAX9206 AN-1058 abstract for wireless communication system and networks high-speed lvds transceiver
Text: Maxim > App Notes > Basestations/Wireless Infrastructure High-Speed Interconnect Interface Circuits Keywords: LVDS, low voltage, differential signaling, signalling, lvds, EIA/TIA-644, 3G, signal distribution, clock distribution, W-CDMA, EDGE, Apr 17, 2002
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EIA/TIA-644,
CDMA2000,
EIA/TIA-644
cdma2000®
MAX9205
MAX9206
MAX9150
10-Port
MAX9152
800Mbps,
AN1058
AN-1058
abstract for wireless communication system and networks
high-speed lvds transceiver
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QFN56 Datasheet
Abstract: ST3DV520QTR JESD97 QFN56 QFN56 footprint QFN-56
Text: ST3DV520 High bandwidth analog switch with 16-to-8 bit MUX/DEMUX Preliminary Data Features • Low RON: 5.5 Ω typical ■ VCC operating range: 3.0 to 3.6 V ■ Low current consumption: 20 µA ■ ESD HBM model: > 2 kV ■ Channel on capacitance: 7.5 pf typical
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ST3DV520
16-to-8
QFN56
ST3DV520
QFN56 Datasheet
ST3DV520QTR
JESD97
QFN56
QFN56 footprint
QFN-56
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TP31C
Abstract: DS3131 DS3134 LA10 LA12 TD39 811B
Text: DALLAS SEMICONDUCTOR DS3131 Preliminary Data Sheet V2 January 26, 1999 DALLAS SEMICONDUCTOR DS3131 BoSS Bit SynchronouS HDLC CONTROLLER 40 Port / 40 Channel HDLC Controller with Option for Local Bus Access Preliminary Data Sheet Version 2 January 26, 1999
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DS3131
DS3131
164Mbps
132Mbps.
50MHz
33MHz.
DS3131.
TP31C
DS3134
LA10
LA12
TD39
811B
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TP31C
Abstract: 083C Cables datasheet rh16c RH25CR hdlc 11-B DS3131 TD39 TH21C rbp2
Text: DEMO KIT AVAILABLE DS3131 BoSS 40-Port, Unchannelized Bit-Synchronous HDLC www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS3131 bit-synchronous BoSS HDLC controller can handle up to 40 channels of highspeed, unchannelized, bit-synchronous HDLC. The on-board DMA has been optimized for
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DS3131
40-Port,
DS3131
DS3131.
TP31C
083C Cables datasheet
rh16c
RH25CR
hdlc
11-B
TD39
TH21C
rbp2
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TH21C
Abstract: TP31C hdlc 11-B DS3131 TD39
Text: DEMO KIT AVAILABLE DS3131 BoSS 40-Port, Unchannelized Bit-Synchronous HDLC www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS3131 bit-synchronous BoSS HDLC controller can handle up to 40 channels of highspeed, unchannelized, bit-synchronous HDLC. The on-board DMA has been optimized for
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DS3131
40-Port,
DS3131
DS3131.
TH21C
TP31C
hdlc
11-B
TD39
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Untitled
Abstract: No abstract text available
Text: DALLAS SEMICONDUCTOR DS3131 Preliminary Data Sheet V2 January 26, 1999 DALLAS SEMICONDUCTOR DS3131 BoSS Bit Synchronous HDLC CONTROLLER 40 Port / 40 Channel HDLC Controller with Option for Local Bus Access Preliminary Data Sheet Version 2 January 26, 1999
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DS3131
DS3131
164Mbps
132Mbps.
50MHz
33MHz.
DS3131.
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TP31C
Abstract: r02f Boss NS-2 PAB1 td33 LDO DS3131 DS3134 LA10 LA12 TD39
Text: DALLAS SEM ICONDUCTOR DS3131 Preliminary Data Sheet V2 January 26, 1999 DALLAS SEMICONDUCTOR DS3131 BoSS Bit Synchronous HDLC CONTROLLER 40 Port / 40 Channel HDLC Controller with Option for Local Bus Access Preliminary Data Sheet Version 2 January 26, 1999
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DS3131
164Mbps
132Mbps.
50MHz
33MHz.
DS3131.
TP31C
r02f
Boss NS-2
PAB1
td33 LDO
DS3134
LA10
LA12
TD39
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