74F74
Abstract: inmos transputer T225 transputer Inmos t805 FP 8022 74F04 800E 801C T222 T225
Text: IMS T225 16-bit transputer FEATURES H 16 bit architecture H 33 ns internal cycle time H 30 MIPS peak instruction rate H Debugging support H 4 Kbytes on-chip static RAM H 60 Mbytes/sec sustained data rate to internal memory H 64 Kbytes directly addressable external memory
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16-bit
74F74
inmos transputer T225
transputer
Inmos t805
FP 8022
74F04
800E
801C
T222
T225
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FPB33
Abstract: FPB35
Text: 224-225.qxp 7/22/2010 3:02 PM Page 224 Pushbutton Series Fiberglass Enclosures Pushbutton Series The Cooper Crouse-Hinds Pushbutton Series offer a solution for applications requiring an enclosure with multiple pre-drilled openings for pushbuttons available in 30mm and 22mm configurations. The
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FPBM320
FPBM325
FPB33
FPB35
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FPB32
Abstract: k 319 FPB33 FMP0606C FMP12 FMP1210
Text: Fiberglass Enclosures Pushbutton Series 5E The Cooper Crouse-Hinds Pushbutton Series offer a solution for applications requiring an enclosure with multiple pre-drilled openings for pushbuttons available in 30mm and 22mm configurations. The notched keyhole design and the ability to order up to 25 holes,
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prot24
FPBM320
FPBM325
FPB32
k 319
FPB33
FMP0606C
FMP12
FMP1210
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T425
Abstract: T400 T414 T800 T805 inmos transputer T425 T800 transputer IMST425
Text: IMS T425 32-bit transputer FEATURES 32 bit architecture 40 ns internal cycle time 25 MIPS peak instruction rate Pin compatible with IMS T805, IMS T800, IMS T400 and IMS T414 Debugging support 4 Kbytes on-chip static RAM System Services 100 Mbytes/sec sustained data rate to internal
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32-bit
T425
T400
T414
T800
T805
inmos transputer T425
T800 transputer
IMST425
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74F04
Abstract: 74F74 800E 801C T222 T225 T225E Inmos T222
Text: IMS T225 16-bit transputer FEATURES 16 bit architecture 33 ns internal cycle time 30 MIPS peak instruction rate Debugging support 4 Kbytes on-chip static RAM 60 Mbytes/sec sustained data rate to internal memory 64 Kbytes directly addressable external memory
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16-bit
74F04
74F74
800E
801C
T222
T225
T225E
Inmos T222
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CA08102001E
Abstract: rk 49 diode E34KFB
Text: Pushbuttons & Indicating Lights 47-1 Pushbuttons & Indicating Lights March 2008 Contents Description Page Toggle Switches — E10 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Toggle Switches — E10E Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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10250T
CA08102001E
CA08102001E
rk 49 diode
E34KFB
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T222 transputer
Abstract: 74F74 800E 801C T222 T225 IMST222 T225E
Text: IMS T225E 16-bit transputer – Extended temperature FEATURES 16 bit architecture 50 ns internal cycle time 20 MIPS peak instruction rate Debugging support 4 Kbytes on-chip static RAM 40 Mbytes/sec sustained data rate to internal memory 64 Kbytes directly addressable external memory
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T225E
16-bit
T222 transputer
74F74
800E
801C
T222
T225
IMST222
T225E
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Inmos t805
Abstract: IMS T805-F20E T425 T800 IMST800 21-F5 REAL32
Text: IMS T805E 32-bit floating-point transputer – Extended temperature FEATURES APPLICATIONS Scientific and mathematical applications High speed multi processor systems High performance graphics processing – HUD/HDD displays Supercomputers Workstations and workstation clusters
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T805E
32-bit
Inmos t805
IMS T805-F20E
T425
T800
IMST800
21-F5
REAL32
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inmos T414
Abstract: inmos T400 12u-1919-g19 25f5 T400 600 inmos transputer T425 T400 clock T800 transputer AD T805 IMS T414
Text: IMS T400 Low cost 32-bit transputer FEATURES H 32 bit architecture H 50 ns internal cycle time H 20 MHz only H 20 MIPS peak instruction rate H 10 MIPS sustained instruction rate H Pin compatible with IMS T805, IMS T800, IMS T425 and IMS T414 H 2 Kbytes on-chip static RAM
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32-bit
inmos T414
inmos T400
12u-1919-g19
25f5
T400 600
inmos transputer T425
T400 clock
T800 transputer
AD T805
IMS T414
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T801
Abstract: speedo meter N10E inmos transputer T800 TIN30 T800 transputer T801-20 2AF3 w188
Text: 127 IMS T801 transputer □ Preliminary Data FEATURES 32 bit architecture 33 ns internal cycle time 30 MIPS peak instruction rate 4.3 Mflops (peak) instruction rate Debugging support 64 bit on-chip floating point unit which conforms to IEEE 754 4 Kbytes on-chip static RAM
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MIL-STD-883C
IMST801
T801-G20S
T801-G25S
T801-G30S
T801-G20M
T801
speedo meter
N10E
inmos transputer
T800
TIN30
T800 transputer
T801-20
2AF3
w188
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ic t805
Abstract: IMS T805-F20E inmos transputer inmos transputer T225 T425 T800 t225 Inmos t805 IMS T805-G20E MEMAD11
Text: SGS-THOMSON IMS T805E •HI 32-bit floating-point transputer - Extended temperature EATURES 32 bit architecture 50 ns internal cycle time 20 MIPS peak instruction rate 2.8 Mflops (peak) instruction rate Pin compatible with IMS T800 Floating Point Unit Debugging support
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T805E
32-bit
ic t805
IMS T805-F20E
inmos transputer
inmos transputer T225
T425
T800
t225
Inmos t805
IMS T805-G20E
MEMAD11
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T225E
Abstract: imst225
Text: _ 16-bit transputer FEATURES • 16 bit architecture ■ 33 ns internal cycle time ■ 30 MIPS peak instruction rate ■ Debugging support ■ 4 Kbytes on-chip static RAM ■ 60 Mbytes/sec sustained data rate to internal memory ■
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16-bit
64rrs
71E1237
T225E
imst225
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imst400
Abstract: 25f0 T222 transputer FP 1117 aj T400 clock FP 801 transputer T222 T225 inmos transputer T225
Text: SGS-THOMSON IMS T225 L K g lT IM M ! 16 -bit transputer EATURES 16 bit architecture 33 ns internal cycle tim e 30 M IPS pea k instruction rate D ebugging support 4 Kbytes on-chip static RAM 60 M bytes/sec sustained data rate to internal m em ory 64 Kbytes directly addressable external m em ory
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16-bit
IMST400
25f0
T222 transputer
FP 1117 aj
T400 clock
FP 801
transputer
T222
T225
inmos transputer T225
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FP 1117 aj
Abstract: a9yv T222 transputer 2BF4 T222 inmos transputer T225 200ppm 2p23 IMST400
Text: SGS-THOMSON IMS T225E 16-bit transputer - Extended temperature FEATURES • 16 bit architecture ■ 50 ns internal cycle tim e ■ 20 M IPS peak instruction rate ■ D ebugging support ■ 4 Kbytes on-chip sta tic RAM ■ 40 M bytes/sec sustained data rate to internal m em ory
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T225E
16-bit
IMST400
FP 1117 aj
a9yv
T222 transputer
2BF4
T222
inmos transputer T225
200ppm
2p23
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T400 600
Abstract: IMS T414
Text: Low cost 32-bit transputer FEATURES • 32 bit architecture ■ 50 ns internal cycle time ■ 20 MHz only ■ 20 MIPS peak instruction rate ■ 10 MIPS sustained instruction rate ■ Pin compatible with IMS T805, IMS T800, IMS T425 and IMS T414 ■ 2 Kbytes on-chip static RAM
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32-bit
T400 600
IMS T414
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T225E
Abstract: ST225
Text: w # S G S -m O M S O N IMS T225E 16-bit transputer - Extended temperature FEATURES • 16 bit architecture ■ 50 ns internal cycle time ■ 20 MIPS peak instruction rate ■ Debugging support ■ 4 Kbytes on-chip static RAM ■ 40 Mbytes/sec sustained data rate to internal memory
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T225E
16-bit
IMST400
T225E
ST225
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Untitled
Abstract: No abstract text available
Text: S G S -T H O M S O N S IMS T225E s L lP T M lM i 16-bit transputer - Extended temperature FEATURES H 16 bit architecture H 50 ns internal cycle time H 20 MIPS peak instruction rate H Debugging support H 4 Kbytes on-chip static RAM H 40 Mbytes/sec sustained data rate to internal
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T225E
16-bit
7T21237
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AD T805
Abstract: B50R MEMAD11 T805 IMS T805-F25S IMST805 transputer Inmos t805 inmos transputer T225 inmos transputer T425
Text: 32-bit floating-point transputer FEATURES • 32 bit architecture ■ 40 ns internal cycle time ■ 25 MIPS peak instruction rate ■ 3.6 Mflops (peak) instruction rate ■ ■ Pin compatible with IMS T800, IMS T425, IMS T400 and IMS T414 Debugging support
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32-bit
AD T805
B50R
MEMAD11
T805
IMS T805-F25S
IMST805
transputer
Inmos t805
inmos transputer T225
inmos transputer T425
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t425
Abstract: SGS thomson power schottky 8000000C sgs thomson 23-F1 KJH T6 IMST425 inmos transputer T425
Text: w # S G S -T H O M S O N IM < 5 , kT # D ïiin g M iiiL iK g T Â E g n e i ,M & _ T 4 2 5 32-bit transputer FEATURES 32 bit architecture 40 ns internal cycle time 25 MIPS peak instruction rate Pin compatible with IMS T805, IMS T800, IMST400 and IMS T414
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32-bit
MST400
PGA/84pin
PLCC/100
t425
SGS thomson power schottky
8000000C
sgs thomson
23-F1
KJH T6
IMST425
inmos transputer T425
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sbl 20100
Abstract: T425-X25S MEMAD11 inmos transputer T425
Text: ^•7 # DMD g(fii ilL[l(gTO©[i!!in(gI / = T S G S -T H O M S O N IM S T 4 2 5 32-bit transputer FEATURES ■ 32 bit architecture ■ 40 ns internal cycle time ■ 25 MIPS peak instruction rate ■ Pin compatible with IMS T805, IMS T800, IMS T400 and IMS T414
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32-bit
sbl 20100
T425-X25S
MEMAD11
inmos transputer T425
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CQ 2AF1
Abstract: IMST425 IMS T400 Inmos T222
Text: 32-bit transputer FEATURES • 32 bit architecture ■ 40 ns internal cycle time ■ 25 MIPS peak instruction rate ■ Pin compatible with IMS T805, IMS T800, IMS T400 and IMS T414 ■ Debugging support ■ 4 Kbytes on-chip static RAM ■ 100 Mbytes/sec sustained data rate to internal
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32-bit
CQ 2AF1
IMST425
IMS T400
Inmos T222
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Untitled
Abstract: No abstract text available
Text: SGS-THOMSON IMS T225 • H I 16-bit transputer EATURES 16 bit architecture 33 ns internal cycle time 30 MIPS peak instruction rate Debugging support 4 Kbytes on-chip static RAM 60 Mbytes/sec sustained data rate to internal memory 64 Kbytes directly addressable external memory
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16-bit
IMST400
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Untitled
Abstract: No abstract text available
Text: S G S -1 H 0 M S 0 N « t i m i I g ï M a M Ê IMS T400 i Low cost 32-bit transputer FEATURES 32 bit architecture 50 ns internal cycle time 20 MHz only 20 MIPS peak instruction rate 10 MIPS sustained instruction rate Pin compatible with IMS T805, IMS T800, IMS T425
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32-bit
T00b2
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IMSC100
Abstract: IMS T800 CPU STI 7110 transputer LONGSUM LED T9000 u44X IMST9000 Edd 44 inmos transputer
Text: 55 IMS T9000 transputer I . tre y mos Preliminary Information FEATURES Instruction set com patible with the IMS T805 Pipelined superscalar m icro-architecture W orkspace cache Programmable m em ory interface 4 Gbyte physical address space 16 Kbyte instruction and data cache
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T9000
IMSC100
IMS T800
CPU STI 7110
transputer
LONGSUM LED
u44X
IMST9000
Edd 44
inmos transputer
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