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    FLOATING POINT Search Results

    FLOATING POINT Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TMPM4GQF15FG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M4 processor with FPU Core Based Microcontroller/32bit/P-LQFP144-2020-0.50-002 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM4GRF20FG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M4 processor with FPU Core Based Microcontroller/32bit/P-LQFP176-2020-0.40-002 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM4KMFWAFG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M4 processor with FPU Core Based Microcontroller/32bit/P-LQFP80-1212-0.50-003 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM4MMFWAFG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M4 processor with FPU Core Based Microcontroller/32bit/P-LQFP80-1212-0.50-003 Visit Toshiba Electronic Devices & Storage Corporation
    TMPM4NQF10FG Toshiba Electronic Devices & Storage Corporation Arm Cortex-M4 processor with FPU Core Based Microcontroller/32bit/P-LQFP144-2020-0.50-002 Visit Toshiba Electronic Devices & Storage Corporation

    FLOATING POINT Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    Formats

    Abstract: MSP430 48e4 MSP430 format
    Text: MSP430 Family Floating Point Formats Topics G Floating Point Formats G-3 G.1 G.2 Single Precision Format Double Precision Format G-3 G-4 G-1 Floating Point Formats G-2 MSP430 Family MSP430 Family Floating Point Formats 26 Floating Point Formats All MSP430 floating-point formats consist of three fields: an exponent field e , a single-bit


    Original     		MSP430 subtrac-128 80000000h 80800000h 00000000h 83200000h 81500000h Formats 48e4 MSP430 format PDF

    R3000A

    Abstract: functional diagram of ALU R3010A block alu IDT79R3081 R3081 2873 R3010A Integrated Device Technology CFC-1
    Text: R3010A Core RISC FLOATING POINT ACCELERATOR FPA CORE Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • Hardware support of single- and double-precision operations: — Floating-Point Add — Floating-Point Subtract — Floating-Point Multiply


    Original     		R3010A 50MHz R3000A 64-bit 32-bit R3010A functional diagram of ALU block alu IDT79R3081 R3081 2873 R3010A Integrated Device Technology CFC-1 PDF

    D-10

    Abstract: D-12 D-16 DSP96002 3F800000 DSP96002 APPLICATIONS DSP96002 fft
    Text: APPENDIX D D.1 FLOATING-POINT NUMBER STORAGE AND ARITHMETIC D.1.1 General The IEEE standard for binary floating point arithmetic provides for the compatibility of floating-point numbers across all implementations which use the standard by defining bit-level encoding of floating-point numbers.


    Original     		32-bit DSP96002 D-10 D-12 D-16 3F800000 DSP96002 APPLICATIONS DSP96002 fft PDF

    radix-2

    Abstract: ADSP-2100
    Text: 6 One-Dimensional FFTs 6.3 BLOCK FLOATING-POINT SCALING Block floating-point scaling is used to maximize the dynamic range of a fixed-point data field. The block floating-point system is a hybrid between fixed-point and floating-point systems. Instead of each data word having


    Original     		PDF

    C-15

    Abstract: C-16 DSP96002 DSP96002 fft
    Text: APPENDIX C IEEE ARITHMETIC C.1 FLOATING-POINT NUMBER STORAGE AND ARITHMETIC C.1.1 General The IEEE standard for binary floating point arithmetic provides for the compatibility of floating-point numbers across all implementations which use the standard by defining bit-level encoding of floating-point numbers.


    Original     		32-bit DSP96002 C-15 C-16 DSP96002 fft PDF

    ARM FPA

    Abstract: FPA11 ARM FPA10 ARM700 PFPA11ARM TMS 3450 ieee 754 Basic ARM block diagram ARM cpu P700-A
    Text: ARM FPA Overview Floating Point Accelerator The FPA floating point accelerator is a single chip floating point coprocessor for the ARM family of RISC CPUs, significantly enhancing the performance of an ARM based system. The device implements a subset of the ARM floating point instruction set in hardware with the remaining instructions being supported by


    Original     		PDF

    Block Floating Point Implementation

    Abstract: tms320c54x floating point processor a 69258 specifications block diagram of of TMS320C54X radix-4 DIT FFT C code 0C72 SPRA610 n5 st pt 2245 ym 238
    Text: Application Report SPRA610 - December 1999 A Block Floating Point Implementation on the TMS320C54x DSP Arun Chhabra and Ramesh Iyer Digital Signal Processing Solutions ABSTRACT Block floating-point BFP implementation provides an innovative method of floating-point


    Original     		SPRA610 TMS320C54x Block Floating Point Implementation tms320c54x floating point processor a 69258 specifications block diagram of of TMS320C54X radix-4 DIT FFT C code 0C72 n5 st pt 2245 ym 238 PDF

    verilog code for floating point multiplication

    Abstract: vhdl code for cordic cosine and sine vhdl code for cordic VHDL code for floating point addition verilog code for floating point division vhdl code for cordic multiplication program for 8051 16bit square root verilog code for single precision floating point multiplication 8051 16bit addition, subtraction CORDIC sine cosine float altera
    Text: DFPMU Floating Point Coprocessor ver 2.05 OVERVIEW DFPMU is a Floating Point Coprocessor, designed to assist CPU in performing the floating point mathematic computations. DFPMU directly replaces C software functions, by equivalent, very fast hardware operations,


    Original     		DP8051, 32-bit verilog code for floating point multiplication vhdl code for cordic cosine and sine vhdl code for cordic VHDL code for floating point addition verilog code for floating point division vhdl code for cordic multiplication program for 8051 16bit square root verilog code for single precision floating point multiplication 8051 16bit addition, subtraction CORDIC sine cosine float altera PDF

    VHDL code for floating point addition

    Abstract: verilog code for floating point division ARITHMETIC COPROCESSOR processor control unit vhdl code vhdl code 8 bit processor 80C51 APEX20KC APEX20KE DP8051 verilog code for floating point multiplication
    Text: DFPAU Floating Point Arithmetic Coprocessor ver 2.05 OVERVIEW DFPAU is a Floating Point Arithmetic Coprocessor, designed to assist CPU in performing the floating point arithmetic computations. DFPAU directly replaces C software functions, by equivalent, very fast hardware


    Original     		DP8051, 32-bit VHDL code for floating point addition verilog code for floating point division ARITHMETIC COPROCESSOR processor control unit vhdl code vhdl code 8 bit processor 80C51 APEX20KC APEX20KE DP8051 verilog code for floating point multiplication PDF

    SPRS591C

    Abstract: sprufe8 aa t 224 256kb nand flash JESD79-2A pru 10.64 TMS320C6746
    Text: TMS320C6746 SPRS591C – NOVEMBER 2009 – REVISED OCTOBER 2011 www.ti.com TMS320C6746 Fixed/Floating-Point DSP Check for Samples: TMS320C6746 1 TMS320C6746 Fixed/Floating-Point DSP 1.1 Features 12 • Highlights – 375/456-MHz C674x Fixed/Floating-Point


    Original     		TMS320C6746 SPRS591C TMS320C6746 32-/40-Bit) 32-Bit Precision/32-Bit) Precision/64-Bit) SPRS591C sprufe8 aa t 224 256kb nand flash JESD79-2A pru 10.64 PDF

    Untitled

    Abstract: No abstract text available
    Text: TMS320C6746 SPRS591C – NOVEMBER 2009 – REVISED OCTOBER 2011 www.ti.com TMS320C6746 Fixed/Floating-Point DSP Check for Samples: TMS320C6746 1 TMS320C6746 Fixed/Floating-Point DSP 1.1 Features 12 • Highlights – 375/456-MHz C674x Fixed/Floating-Point


    Original     		TMS320C6746 SPRS591C TMS320C6746 375/456-MHz C674x PDF

    DDR2 sdram pcb layout guidelines

    Abstract: No abstract text available
    Text: TMS320C6746 SPRS591C – NOVEMBER 2009 – REVISED OCTOBER 2011 www.ti.com TMS320C6746 Fixed/Floating-Point DSP Check for Samples: TMS320C6746 1 TMS320C6746 Fixed/Floating-Point DSP 1.1 Features 12 • Highlights – 375/456-MHz C674x Fixed/Floating-Point


    Original     		TMS320C6746 SPRS591C TMS320C6746 32-/40-Bit) 32-Bit Precision/32-Bit) Precision/64-Bit) DDR2 sdram pcb layout guidelines PDF

    Untitled

    Abstract: No abstract text available
    Text: TMS320C6746 SPRS591C – NOVEMBER 2009 – REVISED OCTOBER 2011 www.ti.com TMS320C6746 Fixed/Floating-Point DSP Check for Samples: TMS320C6746 1 TMS320C6746 Fixed/Floating-Point DSP 1.1 Features 12 • Highlights – 375/456-MHz C674x Fixed/Floating-Point


    Original     		TMS320C6746 SPRS591C TMS320C6746 375/456-MHz C674x PDF

    80960MC

    Abstract: C90FDAA2
    Text: Floating-Point Operation 7 CHAPTER 7 FLOATING-POINT OPERATION This chapter describes the floating-point processing capabilities of the 80960MC processor. The subjects discussed include the real number data types, the execution environment for floating-point operations, the floating-point instructions, and fault and exception handling.


    OCR Scan     		80960MC C90FDAA2 PDF

    i960TM

    Abstract: 400921FB
    Text: Floating-Point Operation 7 CHAPTER 7 FLOATING-POINT OPERATION This chapter describes the floating-point processing capabilities o f the i960 MC processor. The subjects discussed include the real number data types, the execution environment for floating-point operations, the floating-point instructions and fault and exception handling.


    OCR Scan     		PDF

    tms390

    Abstract: L64811 L64814 TMS390C sun sparc pinout
    Text: LSI LOGIC L64814 Floating-Point Unit FPU Preliminary Description The L64814 Floating-Point Unit (FPU) is a highperformance, CMOS implementation of the SPARC (Scalable Processor ARChitecture) FPU. The FPU combines a floating-point controller w ith a high-throughput floating-point processor


    OCR Scan     		L64814 tms390 L64811 TMS390C sun sparc pinout PDF

    Untitled

    Abstract: No abstract text available
    Text: in te l CHAPTER 7 FLOATING-POINT UNIT The Intel Architecture Floating-Point Unit FPU provides high-performance floating-point processing capabilities. It supports the real, integer, and BCD-integer data types and the floating­ point processing algorithms and exception handling architecture defined in the IEEE 754 and


    OCR Scan     		01fl070fl PDF

    TMS34082

    Abstract: CID20 TMS34082A TMS34082B-40 MSA15-0 TMS34020 emulator
    Text: TMS34082A, TMS34082B GRAPHICS FLOATING-POINT PROCESSOR SCGS001A - D315Q, SEPTEMBER 1988 - REVISED SEPTEMBER 1992 • High-Performance Floating-Point RISC Processor Optimized for Graphics • TWo Operating Modes - Floating-Point Coprocessor for TMS34020 Graphics System Processor


    OCR Scan     		TMS34082A, TMS34082B SCGS001A D315Q, TMS34020 TMS34082 TMS34082A-40, TMS34082B-40 CID20 TMS34082A MSA15-0 TMS34020 emulator PDF

    am29325

    Abstract: H-14 AM29325GC WF023740 ScansUX970 TB000640
    Text: Am29325 32-Bit Floating-Point Processor • Single VLSI device performs high-speed floating-point arithmetic - Floating-point addition, subtraction, and multiplication in a single clock cycle - Internal architecture supports sum-of-products, Newton-Raphson division


    OCR Scan     		Am29325 32-Bit 32-bit, 16-bit WF023790 WF023800 WF023810 16-Bit, H-14 AM29325GC WF023740 ScansUX970 TB000640 PDF

    DSP-3201

    Abstract: No abstract text available
    Text: ANALOG DEVICES 32-Bit IEEE Floating-Point Chipset ADSP-3201/ADSP-3202 FEATURES Complete Chipset Implementing Floating-Point Arithmetic Fully Compatible with IEEE Standard 754 Arithmetic Operations on Three Data Formats: 32-Bit Single-Precision Floating Point


    OCR Scan     		32-Bit ADSP-3211 ADSP-3221 240ns 750mW 144-Lead OOUT31 DSP-3201 PDF

    Cy7C601

    Abstract: tyn 618 P5H2
    Text: PRODUCT DESCRIPTION CYPRESS ~ SEMICONDUCTOR CY7C608 RISC Floating-Point Controller Features • Provides interface between the CY7C601 Integer Unit and CY7C609 Floating-Point Unit • Provides SPARC compatible Floating-Point Arithmetic and registers • Very high performance


    OCR Scan     		CY7C608 CY7C601 CY7C609 CY7C608-33GC CY7C608-25GC tyn 618 P5H2 PDF

    Untitled

    Abstract: No abstract text available
    Text: NOV 2 i « # 1 Am29C325 CMOS 32-Bit Floating-Point Processor > 3 DISTINCTIVE CHARACTERISTICS Single VLSI device performs high-speed single­ precision floating-point arithmetic Floating-point addition, subtraction, and multiplication in a single clock cycle


    OCR Scan     		Am29C325 32-Bit 32-bit, 16-bit Am29325 PDF

    MC68020 Minimum System Configuration

    Abstract: MC68882 MC68881 M68000 64 pin MC68020 M68000 MC68000 MC68008 MC68010 MC68030
    Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC68882 Technical Sum m ary HCMOS Enhanced Floating-Point Coprocessor The MC68882 floating-point coprocessor fully implements the IEEE Standard for Binary Floating-Point A rithm etic 754 for use with the Motorola M68000


    OCR Scan     		MC68882 MC68882 M68000 MC68881, MC68881. MC68020/MC68030 32-bit 68-LEAD MC68020 Minimum System Configuration MC68881 M68000 64 pin MC68020 MC68000 MC68008 MC68010 MC68030 PDF

    Am29325

    Abstract: H-14
    Text: A m 29C 325 CMOS 32-Bit Floating-Point Processor FINAL DISTINCTIVE CHARACTERISTICS • • Single VLSI device performs high-speed single­ precision floating-point arithmetic Floating-point addition, subtraction, and multiplication in a single clock cycle


    OCR Scan     		Am29C325 32-Bit 32-bit, 16-bit Am29325 H-14 PDF