F1F02 Search Results

SMD W2T

Abstract: w2t smd BTS 131 SMD MBA IST DATE SHEET SN54ACT3632
Contextual Info: • fl^bi723 aiiossT ist. ■ SN54ACT3632 512x36x2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY _ _ S G B S310-SEPTEM BER 1996 * Free-Running CLKA and CLKB Can Be Asynchronous or Coincident ► Two Independent 512 x 36 Clocked FIFOs

Contextual Info: ggSi'x jjûfey CMOS SyncBiFIFO 256 x 36 x 2, 512 x 36 x 2, 1024x36x2 IDT723622 ¡DT723642 Integrated Device Technology, Inc. Advance inform ation for the IDT723622 Final for the IDT723632 Advance inform ation for the IDT723642 FEATURES: • Free-running CLKA and CLKB m ay be asynchronous or

Contextual Info: Integrated Device Technology, Inc. CMOS Sync BiFlFO With Bus-Matching 256x36x2, 512x36x2, 1,024x36x2 PRELIMINARY IDT723624 IDT723634 IDT723644 NOTE: There is an errata notice on the last page and the corrections have not been incorporated into this document.

Contextual Info: :bflE D 4025771 0013^43 173 • IDT IDT723632 512 X 36 X 2 CMOS SyncBiFIFO INTEGRATE» DEVICE FEATURES: DESCRIPTION: • Free-running CLKA and CLKB may be asynchronous or coincident • Two independent clocked FIFOs buffering data in oppo­ site directions

1h39

Abstract: itt 2222 SN74ABT3614
Contextual Info: SN74ABT3614 64 x 36 x 2 CLOCKED FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SC B S1 2 6 C -JU N E 1992- R E V IS E D JANUARY 1994 Free-Running CLKA and CLKB Can Be Asynchronous or Coincident TWo Independent 64 x 36 Clocked FIFOs Buffering Data In Opposite Directions

fifo 512 x 32

Abstract: A0A31 A20C A25C A26C A28C SN74ACT3638 512 X 32 SRAM
Contextual Info: SN74ACT3638 512 x 32 x 2 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS228B - JUNE 1992 - REVISED JUNE 1994 Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent 512 x 32 Clocked FIFOs Buffering Data in Opposite Directions Read Retransmit Capability From FIFO on

B27E

Contextual Info: 3.3 VOLT CMOS SyncBiFlFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 PRELIMINARY IDT72V3614 Integrated Device Technology, Inc. FEATURES: • T w o independent clocked FIFOs 64 x 36 storage capacity each buffering data in opposite directions • Supports clock frequencies up to 67 MHz

Contextual Info: SN74ACT7822 512 X 36 X 2 CLOCKED FIRST-IN, FIRST-OUT MEMORY JUNE 1992 Free-Running CLKA and CLKB May Be Asynchronous or Coincident TVro Independent 512 x 36 Clocked FIFOs Buffering Data in Opposite Directions Mailbox Bypass Register for Each FIFO Programmable Almost Full and Almost

lifo

Abstract: lfm 5119
Contextual Info: To all our customers Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations o f Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog

Contextual Info: In tegrated D e vice T e ch n o lo g y , Inc. CMOS Triple Bus SyncFIFOT With Bus-Matching 256x36x2, 512x36x2, 1024x36x2 PRELIMINARY IDT723626 IDT723636 IDT723646 NOTE: The errata notice on the last page describes corrections that have already been added to this document.

Contextual Info: 1dt Integrated Device Technology, Inc. 3.3 VOLT CMOS SyncBiFlFO WITH BUS-MATCHING 256x36x2, 512x36x2, 1,024 x 36 x 2 PRELIMINARY IDT72V3624 IDT72V3634 IDT72V3644 • Master Reset clears data and configures FIFO, Partial Reset clears data but retains configuration settings

sk2 354

Abstract: A12C A14C A15C A25C SN74ACT3622 SN74ACT3632 SN74ACT3642
Contextual Info: SN74ACT3632 512x36x2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS224C - JUNE 1992 - REVISED SEPTEMBER 1995 Free-Running CLKA and CLKB Can Be Asynchronous or Coincident • IRB, ORB, AEB, and AFB Flags Synchronized by CLKB Two Independent 512 x 36 Clocked FIFOs

SN74ABT3612

Abstract: B1494
Contextual Info: SN74ABT3612 64 x 36 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY S C BS129F - JULY 1992 - R EVISED FEBRUARY 1996 EFB, FFB, AEB, and AFB Flags Synchronized by CLKB Passive Parity Checking on Each Port Parity Generation Can Be Selected for Each Port

ic 74247

Abstract: 74247 22z2 A26c A19C A23C A25C A28C A29C SN74ACT3638
Contextual Info: SN74ACT3638 512 x 32 x 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS228C - JUNE 1992 - REVISED SEPTEMBER 1995 Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent 512 x 32 Clocked FIFOs Buffering Data in Opposite Directions

Contextual Info: 3.3 VOLT CMOS SyncBiFlFO 256x36x2, 512x36x2, 1 ,02 4 x3 6 x 2 I dt PRELIMINARY IDT72V3622 IDT72V3632 IDT72V3642 Integrated Device Technology, Inc. FEATURES: • Memory storage capacity: IDT72V3622-256 x 36 x 2 1DT72V3632-512 x 36 x 2 IDT72V3642-1,024 x 36 X 2

A20C

Abstract: A23C A25C A26C SN74ACT3622 SN74ACT3632 SN74ACT3642
Contextual Info: SN74ACT3642 1024x36x2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS440A - JUNE 1994 - REVISED SEPTEMBER 1995 Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent Clocked FIFOs Buffering Data in Opposite Directions Mailbox-Bypass Register for Each FIFO

T7815

Abstract: F1F02
Contextual Info: SN74ABT7815 64 X 36 X 2 CLOCKED FIRST-IN, RRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING S C B S 1 2 6 -JU N E 1992 Free-Running C L K A and CLKB May Be Asynchronous or Coincident EFK, FFA, AEA, and AFA Flags Synchronized by CLK A Two Independent 64 x 36 Clocked FIFOs

Contextual Info: LOW-NOISE AM PLIFIERS [CONT.J MODEL NUMBER OPERATING FREQUENCY GHz] GAIN (dB, Min. GAIN FLATNESS (±dB. Max.] NOISE FIGURE (dB, Max.] OUTPUT POWER (dBm. Min.) VSWR IN/OUT (Max.) DC POWER @ +15 V (mA. Nom.| OUTLINE DRAWING 122586 MODERATE BAND LOW-NOISE AMPLIFIERS (CONT.)

M22122

Abstract: BO-817
Contextual Info: 8 |\ æ \dt Integrated Device Technology, Inc. 3.3 VOLT CMOS TRIPLE BUS SyncFlFO WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 FEATURES: • Memory storage capacity: IDT72V3626-256 x 36 x 2 IDT72V3636-512 x 36 x 2 IDT72V3646-1,024 x 36 x 2

TFK 744

Abstract: A29 SMD marking code TY SMD TFK 19 001 qml-38535 SMD MARKING CODE AEA SMD code marking SOM TFK 731 chip 78b27 tfk 108
Contextual Info: REVISIONS LTR DESCRIPTION DATE YR-MO-DA APPROVED A_ Add "Y" package and updated M. A. Frye_ B Updated boilerplate. Changes to ^ ( REV SHEET REV SHEET q -PB) and V diE -P E )- * 9'9

222Z

Abstract: A20C A23C A28C SN74ACT3622 SN74ACT3632 SN74ACT3642 7526A S563
Contextual Info: SN74ACT3632 512 x 36 x 2 CLOCKED FIRST-IN, FIRST-OUT MEMORY SC AS224B - JUNE 1992 - REVISED SEPTEMBER 1994 IRB, ORB, AEB, and AFB Flags Synchronized by CLKB Low-Power 0.8-Mlcron Advanced CMOS Technology Supports Clock Frequencies up to 67 MHz Free-Running CLKA and CLKB Can Be