MPC860
Abstract: addi
Text: SECTION 8 INSTRUCTION EXECUTION TIMING 8.1 INSTRUCTIONS TIMING LIST The following table lists the instruction execution timing in terms of latency and blockage of the appropriate execution unit. A serializing instruction has the effect of blocking all execution units.
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MPC860
addi
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M68000
Abstract: MCF5102
Text: SECTION 2 EXECUTION PIPELINES This section describes the organization of the MCF5102 instruction and operand execution pipelines and a brief description of the associated registers. 2.1 PIPELINES The MCF5102 is comprised of two tightly coupled execution pipelines. The Instruction Fetch
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MCF5102
M68000
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MPC821
Abstract: MC145474 MC145554 MC68160 MC68360
Text: Communication Processor Module 16.8.16 DSP Execution Times The execution time of a given function is a linear function of the number of taps and iterations specified for that function. It contains an overview for context switch, handling the FD, and initialization. Table 16-20 below lists the execution time for each of the DSP functions.
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DIV16
DIV16
MPC821
MC145474
MC145554
MC68160
MC68360
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MC145474
Abstract: MC145554 MC68160 MC68360 MPC860
Text: Communication Processor Module 16.8.16 DSP Execution Times The execution time of a given function is a linear function of the number of taps and iterations specified for that function. It contains an overview for context switch, handling the FD, and initialization. Table 16-20 below lists the execution time for each of the DSP functions.
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MPC860
MC145474
MC145554
MC68160
MC68360
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bytes and string manipulation of 8086
Abstract: addressing modes 8086 intel 8086 internal architecture INTEL 8086 DATA SHEET register organization of intel 8086 8086 interrupts application memory organization of intel 8086 intel 8086 assembly language free 8086 structure intel 8086
Text: Basic Execution Environment 27 This chapter describes the basic execution environment of an Intel Architecture processor as seen by assembly-language programmers. It describes how the processor executes instructions and how it stores and manipulates data. The parts of the execution environment described here include
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8086 Programmers Reference Manual
Abstract: bytes and string manipulation of 8086 memory organization of intel 8086 intel 8086 internal structure 8086 intel Programmers Reference Manual intel 8086 internal architecture register organization of intel 8086 intel 8086 memory segmentation 8086 interrupts application special pentium registers
Text: Basic Execution Environment 27 This chapter describes the basic execution environment of an Intel Architecture processor as seen by assembly-language programmers. It describes how the processor executes instructions and how it stores and manipulates data. The parts of the execution environment described here include
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TR12
Abstract: No abstract text available
Text: Execution Tracing 23 The embedded Pentium processor family uses special bus cycles to support execution tracing. These bus cycles, which are optional, have a significant impact on overall performance. Execution tracing allows the external hardware to track the flow of instructions as they execute inside the
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XORB 48
Abstract: Jump transistor jst 7E UT80CRH196KD XORB
Text: UTMC Application Note_ UT80CRH196KD Instruction Execution Times in State Times Instructions are listed below by their hexadecimal opcode designator and corresponding mnemonic. The instruction execution times are denoted by their state time equivalent (1 State Time = 2 * XTAL1 period).
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UT80CRH196KD
XORB 48
Jump
transistor jst 7E
XORB
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Untitled
Abstract: No abstract text available
Text: TMP320C50KGD, TMP320LC50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS008C - JULY 1996 - REVISED JUNE 2000 D 25-ns, 35-ns, and 50-ns Single-Cycle D D D D D D Instruction Execution Time for 5-V Operation 50-ns Single-Cycle Instruction Execution Time for 3.3-V Operation
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TMP320C50KGD,
TMP320LC50KGD
SGZS008C
25-ns,
35-ns,
50-ns
16-Bit
1056-Word
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Untitled
Abstract: No abstract text available
Text: TMP320C50KGD, TMP320LC50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS008C - JULY 1996 - REVISED JUNE 2000 D 25-ns, 35-ns, and 50-ns Single-Cycle D D D D D D Instruction Execution Time for 5-V Operation 50-ns Single-Cycle Instruction Execution Time for 3.3-V Operation
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TMP320C50KGD,
TMP320LC50KGD
SGZS008C
25-ns,
35-ns,
50-ns
16-Bit
1056-Word
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TMP320C50KGD
Abstract: TMP320LC50KGD 8405
Text: TMP320C50KGD, TMP320LC50KGD DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIE SGZS008B – JULY 1996 – REVISED JUNE 1999 D D D D D D D 35-ns and 50-ns Single-Cycle Instruction Execution Time for 5 V Operation 50-ns Single-Cycle Instruction Execution Time for 3.3 V Operation
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TMP320C50KGD,
TMP320LC50KGD
SGZS008B
35-ns
50-ns
16-Bit
056-Word
TMP320C50KGD
TMP320LC50KGD
8405
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300025
Abstract: FR60
Text: Fujitsu Microelectronics Europe Application Note MCU-AN-300025-E-V11 FR FAMILY 32-BIT MICROCONTROLLER FR60 FAMILY ISR DOUBLE EXECUTION APPLICATION NOTE Interrupt service routine double execution Revision History Revision History Date 2006-03-14 2006-03-22
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MCU-AN-300025-E-V11
32-BIT
300025
FR60
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FR60
Abstract: No abstract text available
Text: Fujitsu Microelectronics Europe Application Note MCU-AN-300025-E-V12 FR FAMILY 32-BIT MICROCONTROLLER FR60 FAMILY ISR DOUBLE EXECUTION APPLICATION NOTE Interrupt service routine double execution Revision History Revision History Date 2006-03-14 2006-03-22
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MCU-AN-300025-E-V12
32-BIT
FR60
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pipeline in core i3
Abstract: DSP56300 bscc core i3 addressing modes
Text: Appendix B INSTRUCTION EXECUTION TIMING B-1 INTRODUCTION This section describes the various aspects of execution timing analysis for each instruction mnemonic and for various instruction sequences. The section consists of the following tables and information:
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DSP56300
pipeline in core i3
bscc
core i3 addressing modes
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Untitled
Abstract: No abstract text available
Text: SHARP SM8311/SM8313/SM8314/SM8315 The SM83CPU core uses pipeline method to speed instruction execution. With this method, OP Exceptions are the memory access instruction and jump instruction : while in the execution cycle of code fetching cycle and execution cycle are
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SM8311/SM8313/SM8314/SM8315
SM83CPU
SM8311/13
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M68000
Abstract: MC68030 TEA4 bd326 BD164
Text: SECTION 11 INSTRUCTION EXECUTION TIMING This section describes the instruction execution and operations table searches, etc. of the MC68030 in terms of external clock cycles. It provides accurate execution and operation timing guidelines but not exact timings for every possible circumstance. This approach is
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MC68030
MC68030.
M68000
TEA4
bd326
BD164
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M68020
Abstract: D3232 dN 823
Text: SECTION 8 INSTRUCTION EXECUTION TIMING This section describes the instruction execution and operations table searches, etc. of the MC68020/EC020 in terms of external clock cycles. It provides accurate execution and operation timing guidelines but not exact timings for every possible circumstance. This
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MC68020/EC020
MC68020/EC020.
M68020
D3232
dN 823
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80960MC
Abstract: No abstract text available
Text: Execution Environment 3 CHAPTER 3 EXECUTION ENVIRONMENT This chapter describes how the 80960MC processor executes instructions and how it stores and manipulates data. The parts of the execution environment that are discussed include the address space, the register model, the instruction pointer, and the arithmetic controls.
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80960MC
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Untitled
Abstract: No abstract text available
Text: Execution Environment 3 CHAPTER 3 EXECUTION ENVIRONMENT This chapter describes how the i960 MC processor stores and executes instructions and how it stores and manipulates data. The parts of the execution environment that are discussed include the address space, the register model, the instruction pointer and the arithmetic
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"tape reader"
Abstract: 8X300
Text: FEATURES • Totally self-contained with keyboard alpha-numeric display, tape reader, TTY output • Dual Microcontrollers: one to run instru ment, one dedicated to execute user’s program • Real time instruction execution • Control of program execution-Halt
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MPEG 1 Audio Compression
Abstract: E0400 8 bit barrel shifter zoran zr
Text: ZfêRAN ZR38001 PROGRAMMABLE DIGITAL SIGNAL PROCESSOR PRELIMINARY FEATURES • High Performance Powerful Address Generation - ■ - 33 MIPs execution of multiple operation 32-bit instruction words - Single-cycle execution of three-data-operand instructions
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ZR38001
32-bit
16-word
1024-point
DS38001
MPEG 1 Audio Compression
E0400
8 bit barrel shifter
zoran zr
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XXXW
Abstract: No abstract text available
Text: SECTION 9 INSTRUCTION EXECUTION TIMING 5200 SERIES ONLY This section presents ColdFire 5200 Series processor instruction execution times in terms of processor core clock cycles. The number of operand references for each instruction is also included, enclosed in parentheses following the number of clock cycles. Each timing
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MCF5200
XXXW
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MC68060
Abstract: M68000 M68060 M680X0 MOVE16 pipeline synchronization
Text: SECTION 10 INSTRUCTION EXECUTION TIMING This section details the MC68060 instruction execution times in terms of processor clock cycles and the superscalar architecture. The number of operand cycles for each instruction is also included, enclosed in parentheses following the number of clock cycles. Timing
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MC68060
M68060
M68000
M680X0
MOVE16
pipeline synchronization
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S320C50
Abstract: AD322 TMS32OC5x
Text: TMS320C5X, TMS320LC5X DIGITAL SIGNAL PROCESSORS I S PR S030-APRIL 1995 | • Powerful 16-Bit TMS320C5X CPU • 20-, 25-, 35-, and 50-ns Single-Cycle Instruction Execution Time for 5-V Operation • 25-, 35-, and 50-ns Single-Cycle Instruction Execution Time for 3-V Operation
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TMS320C5X,
TMS320LC5X
16-Bit
TMS320C5X
50-ns
S320C50
AD322
TMS32OC5x
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