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    EPLD Search Results

    EPLD Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    EP610DI-30 Rochester Electronics LLC EP610 - Classic Family EPLD, Logic,300 Gates,16 Macrocells Visit Rochester Electronics LLC Buy
    EP610PC-35 Rochester Electronics LLC EP610 - Classic Family EPLD, Logic,300 Gates,16 Macrocells Visit Rochester Electronics LLC Buy
    EP910LI-30 Rochester Electronics LLC EP910 - Classic Family EPLD, Logic,450 Gates,24 Macrocells Visit Rochester Electronics LLC Buy
    EP610SC-20 Rochester Electronics LLC EP610 - Classic Family EPLD, Logic,300 Gates,16 Macrocells Visit Rochester Electronics LLC Buy
    EP1810LC-35 Rochester Electronics LLC EP1810 - Classic Family EPLD, Logic, 900 Gates, 48 Macrocells, 35ns, Commercial Visit Rochester Electronics LLC Buy
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    EPLD Price and Stock

    Infineon Technologies AG BTG70902EPLDAUGHBRDTOBO1

    BTG7090-2EPL DAUGH BRD
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    DigiKey BTG70902EPLDAUGHBRDTOBO1 Bulk 3 1
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    Mouser Electronics BTG70902EPLDAUGHBRDTOBO1 24
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    Infineon Technologies AG BTG70501EPLDAUGHBRDTOBO1

    BTG7050-1EPL DAUGH BRD
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    Infineon Technologies AG BTG70901EPLDAUGHBRDTOBO1

    BTG7090-1EPL DAUGH BRD
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    DigiKey BTG70901EPLDAUGHBRDTOBO1 Bulk 3 1
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    Mouser Electronics BTG70901EPLDAUGHBRDTOBO1 24
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    Infineon Technologies AG BTG70502EPLDAUGHBRDTOBO1

    BTG7050-2EPL DAUGH BRD
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    DigiKey BTG70502EPLDAUGHBRDTOBO1 Bulk 3 1
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    Infineon Technologies AG BTS70902EPLDAUGHBRDTOBO1

    BTS7090-2EPL DAUGH BRD
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    DigiKey BTS70902EPLDAUGHBRDTOBO1 Box 1 1
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    EPLD Datasheets (1)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    EPLD Altera Classic EPLD Data Sheet Original PDF

    EPLD Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    7C344-25

    Abstract: C344 74HC CY7C344 Signal Path Designer C3445
    Text: CY7C344 32-Macrocell MAX EPLD Features tional I/O pins communicate to one logic array block. In the CY7C344 LAB there are 32 macrocells and 64 expander product terms. When an I/O macrocell is used as an input, two expanders are used to create an input path. Even if all of the


    Original     		CY7C344 32-Macrocell CY7C344 28-pin, 300-mil 28-pin 7C344-25 C344 74HC Signal Path Designer C3445 PDF

    74151

    Abstract: 74151 pin connection C3406 74151 PIN DIAGRAM 74151 waveform counter schematic diagram 74161 programmer EPLD 22v10 5192JM 74151 multiplexer
    Text: 1CY 7C34 0 fax id: 6100 EPL D Family CY7C340 EPLD Family Multiple Array Matrix High-Density EPLDS Features tion of innovative architecture and state-of-the-art process, the MAX EPLDs offer LSI density without sacrificing speed. • Erasable, user-configurable CMOS EPLDs capable of


    Original     		CY7C340 CY7C34X) 65-micron CY7C34XB) 74151 74151 pin connection C3406 74151 PIN DIAGRAM 74151 waveform counter schematic diagram 74161 programmer EPLD 22v10 5192JM 74151 multiplexer PDF

    31-oq

    Abstract: 7C342-25 CY7C342-35HMB 7C342-35 CY7C342 CY7C342B OQ11
    Text: CY7C342 CY7C342B rif CYPRESS 128-Macrocell M AX EPLD Features Functional Description • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology CY7C342


    OCR Scan     		CY7C342 CY7C342B 128-Macrocell CY7C342) 65-micron CY7C342B) 68-pin CY7C342/CY7C342B CY7C342/ CY7C342B 31-oq 7C342-25 CY7C342-35HMB 7C342-35 OQ11 PDF

    EPLD 5128

    Abstract: EPM5128-1 K942
    Text: EPM5128 EPLD Features □ □ □ □ □ H igh-density, 128-macrocell, general-purpose MAX 5000 EPLD High-speed multi-LAB architecture t PD as fast as 25 ns Counter frequencies up to 50 MHz Pipelined data rates up to 62.5 MHz 256 shareable expander product terms "expanders" allowing over


    OCR Scan     		EPM5128 128-macrocell, 68-pin ALTED001 EPLD 5128 EPM5128-1 K942 PDF

    7400series

    Abstract: cmos logic 7400 series 7400 family TTL 7400-series EPM5016
    Text: The Complete Industry-Standard Programm able Logic Family MAX 5000 EPLDs 384 EPM5192 tpp = 25 ns - C/> 0> .c o 3 08 EPM5128 tpp —25 ns 256 CO Q. A EPM5130 tpp —25 ns O / ca> D EPM5064, tPD = 25 ns 128 ▲ EPM5032, tPD = 15 ns 64 ▲ EPM5016, tPD = 15 ns


    OCR Scan     		EPM5192 EPM5128 EPM5130 EPM5064, EPM5032, EPM5016, 20-pin 100-pin 500-gate 7400series cmos logic 7400 series 7400 family TTL 7400-series EPM5016 PDF

    Untitled

    Abstract: No abstract text available
    Text: AN Ù 1=! n ^ !S \ Contents September 1991 Section 5 STG & SAM EPLDs STG & SAM EPLDs: Synchronous State M achine & W aveform G eneration D evices. 189 EPS464 STG EPLD: Synchronous Tim ing G e n e ra to r.191


    OCR Scan     		EPS464 EPS448 PDF

    Untitled

    Abstract: No abstract text available
    Text: /A^b Contents September 1991 Section 4 MAX 7000 EPLDs MAX 7000 EPLD Overview: H igh-Perform ance, High-Pin-Count D e v ice s. 179 A lte ra C o rp o ra tio n


    OCR Scan     		PDF

    EPM5130

    Abstract: 100-Pin Package Pin-Out Diagram D2-3401 EPM 5130
    Text: EPM5130 EPLD □ □ Features □ □ □ □ □ □ □ High-density, 128-macrocell, general-purpose MAX 5000 EPLD 128 m acrocells optim ized for pin-intensive applications, easily integrating over 60 TTL MSI and SSI components High-speed multi-LAB architecture


    OCR Scan     		EPM5130 128-macrocell, 32-bit 16-bit 100-pin 84-pin in100-Pin ALTED001 100-Pin Package Pin-Out Diagram D2-3401 EPM 5130 PDF

    EP910T

    Abstract: altera EP910 EP910-T
    Text: EP910T EPLD Features □ □ a □ □ High-performance, 24-macrocell Classic EPLD Combinatorial speeds with tPD = 30 ns Counter frequencies up to 33 MHz Pipelined data rates up to 41 MHz Programmable I/O architecture with up to 36 inputs or 24 outputs Pin-, function-, and programming file-compatible with Altera's EP910


    OCR Scan     		EP910T 24-macrocell EP910 EP910A 44-pin 40-pin ALTED001 altera EP910 EP910-T PDF

    EPLD 5128

    Abstract: EPM5120-2
    Text: EPM5128 EPLD Features □ □ H ig h -d en sity 128-m acrocell g en era l-p u rp o se M A X 5000 EPLD 256 sh areab le ex p a n d e r p ro d u ct term s th at allow ov er 32 p ro d u ct term s in a sin gle m acro cell H ig h -sp eed m u lti-L A B a rch itectu re


    OCR Scan     		EPM5128 128-m 68-pin EPLD 5128 EPM5120-2 PDF

    EP1810-35T

    Abstract: ALTERA EP altera EP1810
    Text: Features □ □ □ □ □ □ High-performance, 48-macrocell Classic EPLD Combinatorial speeds with tPD = 20 ns, 25 ns, and 35 ns - Counter frequencies up to 50 MHz Pipelined data rates up to 62.5 MHz Programmable I/O architecture with up to 64 inputs or 48 outputs


    OCR Scan     		48-macrocell EP1810 MIL-STD-883-compliant 68-pin EP1810T EP1810-20T, EP1810-25T, EP1810-35T ALTED001 ALTERA EP altera EP1810 PDF

    J-Lead, QFP ceramic

    Abstract: PQFP 176 J-Lead
    Text: EPM5192A EPLD □ Features □ □ Preliminary Information □ □ □ High-performance, second-generation MAX 5000 EPLD developed on an advanced 0.65-m icron CM OS EPROM process High-speed upgrade for existing EPM 5192 designs High-speed multi-LAB architecture


    OCR Scan     		EPM5192A 74-series 84-pin 100-Pin ALTED001 J-Lead, QFP ceramic PQFP 176 J-Lead PDF

    EP610-30

    Abstract: EP610-35 EP610-25 EP610 EP610-15 EP610-20 EP6101-10 EP610I
    Text: EP610 EPLD Features * • ■ ■ ■ ■ High-performance, 16-macrocell Classic EPLD Combinatorial speeds with tP D as fast as 10 ns Counter frequencies of up to 100 MHz Pipelined data rates of up to 125 MHz Programmable I/O architecture with up to 20 inputs or 16 outputs


    OCR Scan     		EP610 16-macrocell EP610I 24-pin 28-pin EP610 16-bit EP610-30 EP610-35 EP610-25 EP610-15 EP610-20 EP6101-10 PDF

    ep610

    Abstract: EP610-30 EP610-35 EP610-25 EP610-15 EP610-20 EP610I P6101
    Text: EPLD Features H igh -perform an ce, 16-m acrocell Classic EPLD C om binatorial speeds w ith as low as 10 ns C oun ter frequencies of up to 100 M H z Pipelined d ata rates of up to 125 M H z Program m able I / O arch itectu re w ith up to 20 inputs o r 16 ou tp uts


    OCR Scan     		EP610EPLD EP610I, EP600I 24-pin 24-pine 16-bit ep610 EP610-30 EP610-35 EP610-25 EP610-15 EP610-20 EP610I P6101 PDF

    Untitled

    Abstract: No abstract text available
    Text: EPM5064 EPLD Features • ■ ■ ■ ■ ■ ■ High-density, 64-macrocell, general-purpose MAX 5000 EPLD High-speed multi-LAB architecture tpu as fast as 15 ns Counter frequencies up to 83.3 MHz Pipelined data rates up to 100 MHz 128 shareable expander product terms "expanders" allowing over


    OCR Scan     		EPM5064 64-macrocell, 44-pin 16-bit PDF

    L496D

    Abstract: 9l reset CY7C331 ST L11922 0423-J
    Text: CY7C331 -W C Y P R E S S Asynchronous Registered EPLD Features • TWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coining from the I/O pin — Independent product term set,


    OCR Scan     		CY7C331 28-pin CY7C331 -40TMB 28-Lead CY7C331â 40WMB 28-Lead 300-Mil) L496D 9l reset ST L11922 0423-J PDF

    K12J

    Abstract: 100-PIN CY7C346 CY7C346B f 7400
    Text: CY7C346 CY7C346B 5T CYPRESS 128-Macrocell MAX EPLDs Features Functional Description • 128 macrocells in 8 LABs • 20 dedicated inputs, up to 64 bidirec­ tional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology CY7C346


    OCR Scan     		CY7C346 CY7C346B CY7C346) 65-micron CY7C346B) 84-pin 100-pin 128-Macrocell CY7C346/CY7C346B CY7C346/ K12J CY7C346B f 7400 PDF

    C3402

    Abstract: 74151 5128LC-1 74151 PIN DIAGRAM 5128LC-2 74151 8 to 1 74151 pin connection function of 74151 22V10-10C CY7C340
    Text: EPLD CY7C340 EPLD Family Multiple Array Matrix High-Density EPLDs Features • Erasable, user-configurable CMOS EPLDs capable of implementing high-density custom logic functions • 0.8-micron double-metal CMOS EPROM technology CY7C34X • Advanced 0.65-micron CMOS technology to increase


    Original     		CY7C340 CY7C34X) 65-micron CY7C34XB) C3402 74151 5128LC-1 74151 PIN DIAGRAM 5128LC-2 74151 8 to 1 74151 pin connection function of 74151 22V10-10C PDF

    c3431

    Abstract: C3438 c3432 CY7C343 c3435 C343-8
    Text: CY7C343 64-Macrocell MAX EPLD Features • • • • • • The CY7C343 contains 64 highly flexible macrocells and 128 expander product terms. These resources are divided into four Logic Array Blocks LABs connected through the Programmable Inter-connect Array (PIA). There are 8 input pins, one that


    Original     		CY7C343 64-Macrocell CY7C343 44-pin c3431 C3438 c3432 c3435 C343-8 PDF

    EDIF200

    Abstract: XC4013E-3PQ208C industrial pulse generators schematic Lattice PLSI Temic ulc
    Text: IC DIVISION TEMIC Semiconductors ULC Design Checklist To perform the ULC to FPGA or EPLD feasibility study and conversion rapidly and accurately, please fill out the form below and supply the requested material. All questions must be answered. 1. Customer


    Original     		PDF

    Untitled

    Abstract: No abstract text available
    Text: XC7236A 36-Macrocell CMOS EPLD HXILINX Preliminary Product Specifications Features The functional versatility of the traditional programmable logic array architecture is enhanced through additional gating and control functions available in an Arithmetic Logic Unit ALU in each Macrocell. Dedicated fast arith­


    OCR Scan     		XC7236A 36-Macrocell 44-Pin XC7236A PDF

    Untitled

    Abstract: No abstract text available
    Text: flX IU N XC7336 36-Macrocell CMOS EPLD X Preliminary Product Specifications Features General Description • The XC7336 is a member of the Xilinx Dual-Block EPLD family. It consists of four Fast Function Blocks intercon­ nected by a central Universal Interconnect Matrix UIM .


    OCR Scan     		XC7336 36-Macrocell XC7336 ninC44 44-Pin PG144 PQ160 PDF

    Untitled

    Abstract: No abstract text available
    Text: XC7354 54-Macrocell CMOS EPLD Product Specifications Features The Universal Interconnect Matrix connects the Function Blocks to each other and to all input pins, providing 100% connectivity between the Function Blocks. This allows logic functions to be mapped into the Function Blocks and


    OCR Scan     		XC7354 54-Macrocell XC7354 XC7300 PQ100 PG144 PQ160 BG225 WB225 PDF

    Untitled

    Abstract: No abstract text available
    Text: AT18V8Z Features • 20-pin Universal EPLD • Virtually Zero Standby Power • Functional Replacement for Common 20-Pin Programmable Devices Io l = 24 mA • High Performance CMOS EPROM Cell Technology Erasable Reconfigurable 100% Testable • 25 ns and 35 ns Max Propagation Delay Commercial


    OCR Scan     		AT18V8Z 20-pin 300-mil-wlde AT18V8Z-25DC AT18V8Z-25JC AT18V8Z-25PC 20DW3 AT18V8Z-30DI AT18V8Z-30JI PDF