XC3030-70PC84C
Abstract: EPM5128LC EP330PC-15 A1020 transistor A1010B-PL68C EPM5128GM EP330PC15 EP330PC XC3042-70PC84C A1020A-PL84C
Text: ULCt Cross-Reference Matra MHS Cross reference list of devices supported for ULC conversion is not exhaustiv as new devices are added regularly. Additional devices not shown in this list, may also be supported. MHS encourages you to contact your local TEMIC sales representative
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A1010A-PL44C
A1010B-PL44C
ULC/A1010
44-PLCC
A1010A-PL44I
A1010B-PL44I
A1010A-1PL44C
A1010B-1PL44C
A1020A-1PL44C
XC3030-70PC84C
EPM5128LC
EP330PC-15
A1020 transistor
A1010B-PL68C
EPM5128GM
EP330PC15
EP330PC
XC3042-70PC84C
A1020A-PL84C
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Device-List
Abstract: cf745 04 p 24LC211 lattice im4a3-32 CF775 MICROCHIP 29F008 im4a3-64 ks24c01 ep320ipc ALL-11P2
Text: Device List Adapter List Converter List for ALL-11 JUL. 2000 Introduction T he Device List lets you know exactly which devices the Universal Programmer currently supports. The Device List also lets you know which devices are supported directly by the standard DIP socket and which
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ALL-11
Z86E73
Z86E83
Z89371
ADP-Z89371/-PL
Z8E000
ADP-Z8E001
Z8E001
Device-List
cf745 04 p
24LC211
lattice im4a3-32
CF775 MICROCHIP
29F008
im4a3-64
ks24c01
ep320ipc
ALL-11P2
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TCA780
Abstract: TFK U 111 B TFK U 4614 B TFK S 186 P TFK U 217 B TFK BP w 41 n TFK BPW 41 N Tfk 880 TFK 148 TDSR 5150 G
Text: Industry Part Number 1N3245 1N3611GP 1N3612GP 1N3613GP 1N3614GP 1N3725 1N3957GP 1N4001GP 1N4002GP 1N4003GP 1N4004GP 1N4005GP 1N4006GP 1N4007GP 1N4245GP 1N4246GP 1N4247GP 1N4248GP 1N4249GP 1N4678.1N4717 1N4728A.1N4761A 1N4933GP 1N4934GP 1N4935GP 1N4936GP
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1N3245
1N3611GP
1N3612GP
1N3613GP
1N3614GP
1N3725
1N3957GP
1N4001GP
1N4002GP
1N4003GP
TCA780
TFK U 111 B
TFK U 4614 B
TFK S 186 P
TFK U 217 B
TFK BP w 41 n
TFK BPW 41 N
Tfk 880
TFK 148
TDSR 5150 G
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PDN0518
Abstract: EPM7128STC100-15 EP610ILC-10 EP610IPC-10 EPM7160STC100-10 EPM7064SLC44-10 EPM7064SLC44-10F EPM7128STC100 EP20K100BC356-2X ALTERA EPM7128STC100-15
Text: Page 1 of 4 PRODUCT DISCONTINUANCE NOTIFICATION PDN0518 Change Description: Altera will be discontinuing the APEX II, APEX 20K, APEX 20KC, APEX 20KE, Classic™, FLEX 8000, MAX® 3000A, MAX 7000, MAX 7000B, and MAX 7000S ordering codes listed in Tables 1 through 10.
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PDN0518
7000B,
7000S
7000B
EPM7032BUC49-3A
EPM7064SLC44-10F
EPM7064SLC44-10*
EPM7128STC100-15F
EPM7128STC100-15*
PDN0518
EPM7128STC100-15
EP610ILC-10
EP610IPC-10
EPM7160STC100-10
EPM7064SLC44-10
EPM7064SLC44-10F
EPM7128STC100
EP20K100BC356-2X
ALTERA EPM7128STC100-15
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EP910dm
Abstract: EP910PC-30 EP910DC-40 EP1810LC-35 EP1810LC-20 EP610PC-15 Programming EP610DI-30 EP910JI-35 EP610IDC25 EP610SC-15
Text: Classic EPLD Family May 1999, ver. 5 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family with logic densities of 300 to 900 usable gates see Table 1 Device erasure and reprogramming with non-volatile EPROM configuration elements
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EP610LC-15
EP610LC-25
EP610ILI-12
EP610PC-15
EP610PI-30
EP910dm
EP910PC-30
EP910DC-40
EP1810LC-35
EP1810LC-20
EP610PC-15 Programming
EP610DI-30
EP910JI-35
EP610IDC25
EP610SC-15
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ulc xc3030
Abstract: PQFP 176 Xilinx XC3090 altera EP300 EPM7128 Temic ulc xc3030 EPM7128 PLCC PLSI2032 Actel A1020 PLUS405
Text: ULC Reference Guide This reference guide lists most devices available for conversion. This list is not exhaustive, as new devices are added regularly. Additional devices not shown in this list may also be supported. Updated versions are available on the TEMIC web site. Check with factory if
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ULC/A1010
ULC/A1020
ulc xc3030
PQFP 176
Xilinx XC3090
altera EP300
EPM7128
Temic ulc xc3030
EPM7128 PLCC
PLSI2032
Actel A1020
PLUS405
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Untitled
Abstract: No abstract text available
Text: m ft i m intpl ¡PLD910 FAST 24-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP900, EP910, EP910A, 85C090 and 5C090 • tpo 12 ns, 62.5 MHz w/Feedback, Clock to Output 8 ns ■ Extensive Software and Programming Support via Intel and Third-Party Tools
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PLD910
24-MACROCELL
EP900,
EP910,
EP910A,
85C090
5C090
PLD910
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EPLD
Abstract: EP910A SR flipflops EP310 EP910
Text: E P 910 E P L D Features □ □ □ □ □ □ □ □ General Description H igh-perform ance 24-m acroeell EPLD Com binatorial speeds with t?D = 30 ns Counter frequencies up to 33 MHz Pipelined data rates up to 41 M H z Pin-, function-, and JEDEC-File-com patible with A ltera's EP910A and
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EP910
EP910A
EP910T
44-pin
40-pin
BP910
EP910
EPLD
SR flipflops
EP310
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npld910-25
Abstract: 85C090 P85C090 p85c090-25 PLD910-15 TN85C090-25 INTEL PLD910 npld intel PLD NPLD910-12
Text: INTEL CORP MEMORY/PL] / SbE J> m 4 A 2 b l 7 b 0 0 7 7 5 1 7 514 • I T L 2 ir r te l. P W io - 1 ^ - 0 ^ ¡PLD910/85C090 FAST 24-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP900, EP910, EP910A, 85C090 and 5C090 Extensive Software and Programming
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OCR Scan
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PLD910/85C090
24-MACROCELL
EP900,
EP910,
EP910A,
85C090
5C090
IPLD910/85C090
IPLD910
51-C/W
npld910-25
P85C090
p85c090-25
PLD910-15
TN85C090-25
INTEL PLD910
npld
intel PLD
NPLD910-12
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910-A01
Abstract: No abstract text available
Text: EP910A EPLD High-Performance 24-Macrocell Device March 1993, ver. 2 Data Sheet Supplement Features □ □ P relim inary Inform ation □ □ □ □ □ □ Highest-performance 24-macrocell Classic EPLD Combinatorial speeds with tPD = 10 ns Counter frequencies up to 100 MHz
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OCR Scan
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EP910A
24-Macrocell
EP910
EP910T
EP910
24-Macrocell
910-A01
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PDF
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intel PLD
Abstract: INTEL PLD910 PLD910-25
Text: in tj ÌPLD910 FAST 24-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP900, EP910, EP910A, 85C090 and 5C090 • tpD 12 ns, 62.5 MHz w/Feedback, Clock to Output 8 ns ■ Ice = 150 mA Max @ 1 MHz ■ Programmable Low-Power Option for “Standby” Operation; 60 /¿A Typ. in
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OCR Scan
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PLD910
24-MACROCELL
EP900,
EP910,
EP910A,
85C090
5C090
IPLD910
IPLD910
intel PLD
INTEL PLD910
PLD910-25
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85C090
Abstract: No abstract text available
Text: IPKIlLOBilDKIÄKV i n y 85C090-12 24-M ACRO CELL CH M O S jliPLD Function, Pin, and JEDEC Compatible with 5C090, EP900, EP910 and EP910A Extensive Software and Programming Support via Intel and Third-Party Tools tpo 12 ns, 83.3 MHz w/Feedback, Clock to Output 8 ns
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OCR Scan
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85C090-12
5C090,
EP900,
EP910
EP910A
85C090
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Untitled
Abstract: No abstract text available
Text: EP910A EPLD Features Preliminary Information □ □ □ □ □ □ Highest-performance, 24-macrocell Classic EPLD Combinatorial speeds with tPD = 10 ns - Counter frequencies up to 100 MHz - Pipelined data rates up to 125 MHz Fabricated on advanced 0.8-micron CMOS EEPROM technology
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OCR Scan
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EP910A
24-macrocell
EP910
EP910T
44-pin
EP910A1
EP910A-15
EP910A-10,
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85C090
Abstract: N85C090-15 P85C090 P85c090-25 D85C090-25 N85C090-25 P85C090-15 PLD910 TN85C090-25 ipld910
Text: inU . ¡PLD910/85C090 FAST 24-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP900, EP910, EP910A, 85C090 and 5C090 • t PD 12 ns, 62.5 M H z w /F e e d b a c k , C lock to O u tp u t 8 ns ■ E xte n s iv e S o ftw a re an d P ro g ram m in g
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OCR Scan
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PLD910/85C090
24-MACROCELL
EP900,
EP910,
EP910A,
85C090
5C090
IPLD910
N85C090-15
P85C090
P85c090-25
D85C090-25
N85C090-25
P85C090-15
PLD910
TN85C090-25
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Untitled
Abstract: No abstract text available
Text: EP910A EPLD Features □ □ □ □ General Description Altera's EP910A Erasable Programmable Logic Device EPLD is a pincompatible version of the EP910 EPLD. It offers enhanced performance and is available in 600-mil, 40-pin DIP and 44-pin J-lead chip carrier
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OCR Scan
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EP910A
EP910
600-mil,
40-pin
44-pin
24-macrocell
EP910A-25
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EP910T
Abstract: altera EP910 EP910-T
Text: EP910T EPLD Features □ □ a □ □ High-performance, 24-macrocell Classic EPLD Combinatorial speeds with tPD = 30 ns Counter frequencies up to 33 MHz Pipelined data rates up to 41 MHz Programmable I/O architecture with up to 36 inputs or 24 outputs Pin-, function-, and programming file-compatible with Altera's EP910
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OCR Scan
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EP910T
24-macrocell
EP910
EP910A
44-pin
40-pin
ALTED001
altera EP910
EP910-T
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Untitled
Abstract: No abstract text available
Text: Features a General Description Altera's EP910T Erasable Programmable Logic Device EPLD is a lowcost, high-performance version of the EP910 device. This EPLD operates in a turbo mode that is optimized for high-speed applications. The Turbo Bit in the device is preset at the factory. The EP910T EPLD is available in OTP
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EP910T
EP910
40-pin,
600-mil
44-pin
EP910TEPLD
EP910-30T
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PDF
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programming manual EPLD EPS448
Abstract: Altera EPM5128 EPM7064-12 leap u1 EP-900910 PLE3-12a tcl tv circuit altera eplds EP610 "pin compatible" ALTERA MAX 5000
Text: Data Book TENTH ANNIVERSARY A Decade of Leadership A u g u s t 1993 Data Book August 1993 A-DB-0793-01 Altera, MAX, and M A X+PLUS are registered trademarks of Altera Corporation. The following, among others, are trademarks of Altera Corporation: AHDL, M AX+PLUS II, PL-ASAP2, PLDS-HPS, PLS-ADV, PLS-ES, PLS-FLEX8, PLS-FLEX8/H P, PLS-FLEX8/SN , PLS-HPS, PLS-STD, PLS-W S/H P,
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-DB-0793-01
EP330,
EP610,
EP610A,
EP610T,
EP910,
EP910A,
EP910T,
EP1810,
EP1810T,
programming manual EPLD EPS448
Altera EPM5128
EPM7064-12
leap u1
EP-900910
PLE3-12a
tcl tv circuit
altera eplds
EP610 "pin compatible"
ALTERA MAX 5000
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EPM5192L
Abstract: EPM5128L EPM5192J 2-0068-06234 EPM5032L EP910J 821573-1
Text: Selecting Sockets for J-Lead Packages Application Brief 46 September 1991, ver. 4 Introduction EPLD s solve m any of the problem s designers face today. T h e y offer low cost, low power, high reliability, and most im portantly, high integration density. Altera offers w ind ow ed ceram ic and on e -tim e -p rog ra m m a b le
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altera EP910
Abstract: EP910-T IEP910 altera eplds EP910EPLD
Text: t ALTERA 47E CORP D • 05*15372 00020TM - r Tfl? o - ■ c f ALT EP910 EPLDs High-Performance 24-Macrocell Devices Data Sheet September 1991, ver. 2 □ □ Features □ □ □ □ □ □ □ General Description Altera's EP910 Erasable Programmable Logic Devices EPLDs can
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OCR Scan
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00020TM
EP910
24-Macrocell
EP910T
EP910-30T
altera EP910
EP910-T
IEP910
altera eplds
EP910EPLD
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PDF
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altera ep900
Abstract: ep900 24-MACROCELL
Text: EP900 EPLD 24-Macrocell Device June 1993, ver. 1 Data Sheet Supplement Features □ □ □ □ □ □ 24-macrocell Classic EPLD Combinatorial speeds with tPD = 50 ns Counter frequencies up to 20.0 MHz Pipelined data rates up to 23.8 MHz Programmable I/O architecture with up to 36 inputs or 24 outputs
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OCR Scan
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EP900
24-Macrocell
EP910,
EP910A,
EP910T
00D3fcj75
altera ep900
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PDF
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Untitled
Abstract: No abstract text available
Text: / an ù riü r * à \ September 1991, ver. 3 Operating Requirements for EPLDs Data Sheet Introduction A ltera EPLDs co m b in e a u n iq u e a rc h ite c tu re w ith an a d v a n c e d C M O S E PROM proce ss that p r o v id e s ex c eptional p e r f o rm a n c e w ith low p o w er.
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OCR Scan
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PDF
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ep330
Abstract: vhdl code for 4 bit counter vhdl code for sr flipflop EP610 ORDERING EPLD 900
Text: Classic Programmable Logic Device Family Data Sheet August 1993, ver. 1 □ Features □ □ □ □ □ □ □ □ □ Complete EPLD fam ily with logic densities up to 1,800 available gates 900 usable gates . See Table 1. M ultiple 20-pin PAL and GAL replacem ent and integration
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OCR Scan
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20-pin
ALTED001
ep330
vhdl code for 4 bit counter
vhdl code for sr flipflop
EP610 ORDERING
EPLD 900
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PDF
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dpld910
Abstract: pld910 IPLD910-25 DPLD910-15 adf simu 5C090 tcl eprom intel PLD INTEL PLD910 adf compiler
Text: i n t j . ÌPLD910 FAST 24-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP900, EP910, EP91QA, 85C090 and 5C090 m tpo 12 ns, 62.5 MHz w/Feedback, Clock to Output 8 ns • Ice = 150 mA Max @ 1 MHz ■ Programmable Low-Power Option for “Standby” Operation; 60 ju.A Typ. in
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OCR Scan
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PLD910
24-MACROCELL
EP900,
EP910,
EP91QA,
85C090
5C090
IPLD910
IPLD910
dpld910
IPLD910-25
DPLD910-15
adf simu
5C090
tcl eprom
intel PLD
INTEL PLD910
adf compiler
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