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    Intel Corporation EP1S20F484C5

    IC FPGA 361 I/O 484FBGA
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    DigiKey EP1S20F484C5 Tray
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    Intel Corporation EP1S20F484C5N

    IC FPGA 361 I/O 484FBGA
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    Altera Corporation EP1S20F484C5N

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    Quest Components EP1S20F484C5N 2
    • 1 $936.25
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    EP1S20F484C5 Datasheets (4)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    EP1S20F484C5 Altera Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 361 I/O 484FBGA Original PDF
    EP1S20F484C5 Altera Stratix FPGA 20K FBGA-484 Original PDF
    EP1S20F484C5N Altera Embedded - FPGAs (Field Programmable Gate Array), Integrated Circuits (ICs), IC FPGA 361 I/O 484FBGA Original PDF
    EP1S20F484C5N Altera Stratix FPGA 20K FBGA-484 Original PDF

    EP1S20F484C5 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    ADV7174

    Abstract: CCIR-656 EP1C4F324C6 EP1S20F484C5 EP2C20F484C6 EP2S15F484C3 cyclone 2 bt.656 parallel to RGB
    Text: Produces video data that meets the ITU-R BT.601/BT.656 recommendation without the SAV and EAV features TVOUT-CTRL Accepts display data input in three formats: Video Display Controller Core o RGB 24 bits/pixel o RGB 15 bits/pixel o 4:2:2 YUV (YCbCr) Provides a video data analog


    Original     		PDF 601/BT ADV7174/79 CCIR-601 CCIR-656) ADV7174 CCIR-656 EP1C4F324C6 EP1S20F484C5 EP2C20F484C6 EP2S15F484C3 cyclone 2 bt.656 parallel to RGB

    PCN0902

    Abstract: HC220F780NAK HC220F672nan HC210F484NAC XZ-092 HC230F1020BN HC240F1020NBC HC230F1020AW EP2S60F1020C4N EP2SGXF1152AA
    Text: Revision: 1.1.0 PROCESS CHANGE NOTIFICATION PCN0902 ADDITIONAL ASSEMBLY SOURCE AND BILL OF MATERIAL CHANGE FOR ALTERA FLIP CHIP PRODUCTS Change Description This is an update to PCN0902; please see the revision history table for information specific to this


    Original     		PDF PCN0902 PCN0902; PCN0902 HC220F780NAK HC220F672nan HC210F484NAC XZ-092 HC230F1020BN HC240F1020NBC HC230F1020AW EP2S60F1020C4N EP2SGXF1152AA

    "Stratix IV" Package layout information

    Abstract: EP1S25F780C7 EP1S30F780C7 S-51005
    Text: Stratix Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com S5V1-1.2 Copyright 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and


    Original     		PDF EP1S80B956C6 EP1S80B956C7 EP1S80 EP1S80F1020C5 EP1S80F1508C6 EP1S80F1508C7 EP1S80* "Stratix IV" Package layout information EP1S25F780C7 EP1S30F780C7 S-51005

    EP1S25F780C7

    Abstract: EP1S30F780C7
    Text: Section I. Stratix Device Family Data Sheet This section provides designers with the data sheet specifications for Stratix devices. They contain feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference to power


    Original     		PDF EP1S80B956C6 EP1S80B956C7 EP1S80 EP1S80F1020C5 EP1S80F1508C6 EP1S80F1508C7 EP1S80* EP1S25F780C7 EP1S30F780C7

    EP1S40F780C5

    Abstract: EP1S25F780C7 EP1S30F780C7 ep1s20f484c6 EP1S20F484C7
    Text: Stratix December 2002, ver. 3.0 Introduction Preliminary Information Features. Data Sheet The StratixTM family of FPGAs is based on a 1.5-V, 0.13-µm, all-layer copper SRAM process, with densities up to 114,140 logic elements LEs and up to 10 Mbits of RAM. Stratix devices offer up to 28 digital signal


    Original     		PDF 420-MHz EP1S80B956C6 EP1S80B956C7 EP1S80 EP1S80F1020C5 EP1S80F1508C6 EP1S80F1508C7 EP1S80* EP1S40F780C5 EP1S25F780C7 EP1S30F780C7 ep1s20f484c6 EP1S20F484C7

    EP1S20F780C6

    Abstract: EP1S25F780C7 EP1S30F780C7 EP1S20F484C7 3104 303
    Text: Section I. Stratix Device Family Data Sheet This section provides designers with the data sheet specifications for Stratix devices. They contain feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference to power


    Original     		PDF EP1S20B672C6 EP1S20 EP1S20B672C7 EP1S20F484C5 EP1S20F484C6 EP1S20F484C7 EP1S20F672C6 EP1S20F672C7 EP1S20F780C6 EP1S25F780C7 EP1S30F780C7 3104 303

    EP1S25F780C7

    Abstract: EP1S30F780C7
    Text: Section I. Stratix Device Family Data Sheet This section provides designers with the data sheet specifications for Stratix devices. They contain feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference to power


    Original     		PDF EP1S80B956C6 EP1S80B956C7 EP1S80 EP1S80F1020C5 EP1S80F1508C6 EP1S80F1508C7 EP1S80* EP1S25F780C7 EP1S30F780C7