NS32201
Abstract: LK 2816 LK 1623 NS32016 0C16 4C16 C1995 NS32202 NS32203-10 M4116
Text: June 1988 NS32203-10 Direct Memory Access Controller General Description Features The NS32203 Direct Memory Access Controller DMAC is a support chip for the Series 32000 microprocessor family designed to relieve the CPU of data transfers between memory and I O devices The device is capable of packing
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NS32203-10
NS32203
16-bit
NS32201
LK 2816
LK 1623
NS32016
0C16
4C16
C1995
NS32202
M4116
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M68000
Abstract: MC68450 datasheet m68000 M6800 motorola M6800 diode A23 DOWNLOAD FLOPPY DISK DATASHEET FLOPPY DISK DATASHEET M68000-Based "Floppy Disk"
Text: D0-D15 A8-A23 A8/D0-A23/D15 D0-D15 AS MC68450 LDS REQ2 DMAC UDS R/W ACK2 DTACK PCL2 FC0-FC2 3 IRQ REQ3 ACK3 PCL3 AS MEMORY CS AS LDS UDS R/W DTACK FC0-FC2 ERROR AS IACK BEC0BEC2 DTC DONE D0-D15 DS R/W DTACK A1-A23 3 SYSTEM CONTROL IACK CS DECODE BERR HALT
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D0-D15
A8-A23
A8/D0-A23/D15
A1-A23
MC68450
M68000
datasheet m68000
M6800
motorola M6800
diode A23
DOWNLOAD FLOPPY DISK DATASHEET
FLOPPY DISK DATASHEET
M68000-Based
"Floppy Disk"
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Untitled
Abstract: No abstract text available
Text: APRIL 1995 MA31753 PRELIMINARY INFORMATION DS3825-3.2 MA31753 DMA CONTROLLER DMAC FOR USE IN AN MA31750 SYSTEM The MA31753 Direct Memory Access Controller (DMAC) is a peripheral interface circuit design primarily for use with the MA31750 microprocessor. Each DMAC provides up to four
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MA31753
DS3825-3
MA31750
MA31753
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TX39
Abstract: C 4927 TX49 fpu coprocessor TX39-CPU toshiba trace code
Text: TOSHIBA TX39™/TX49™ RISCASIC Cores 32/64-bit MIPS FPU Inst. C ac h e Data C ac h e D S U A PU W BU DMAC G- bus H i gh sp e e d P e r i phe r a l s T X . . C or e M e m or y U se r L ogic I M - Bus Br i dg e TLB G -Bus I nt er f ac e T X C PU U A RT
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TX39TM/TX49TM
32/64-bit
TX39
C 4927
TX49
fpu coprocessor
TX39-CPU
toshiba trace code
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HD64F2376
Abstract: HD64F2378 HD64F2377 HD64F2378R HD6412373R
Text: Section 1 Overview 1.1 Features • High-speed H8S/2000 CPU with an internal 16-bit architecture Upward-compatible with H8/300 and H8/300H CPUs on an object level Sixteen 16-bit general registers 65 basic instructions • Various peripheral functions DMA controller DMAC *1
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H8S/2000
16-bit
H8/300
H8/300H
10-bit
H8S/2376.
H8S/2375,
H8S/2375R,
HD64F2376
HD64F2378
HD64F2377
HD64F2378R
HD6412373R
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Untitled
Abstract: No abstract text available
Text: MN103002A Type MN103002A Command Cache 4 K-byte 2-Way Data Cache 4 K-byte (2-Way) Package (Conventional Package) Minimum Instruction Execution Time QFP160-P-2828F *Lead-free (QFP160-P-2828B) 15 ns (at 3.3 V to lerance = ± 5%, 66 MHz) Interrupts • RESET • IRQ0 to 7 • NMI • Timer 0 to 8 • SIO0 to 5 • DMAC0 to 3 • WDT • System error
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MN103002A
MN103002A
QFP160-P-2828F
QFP160-P-2828B)
16-bit
PX-ICE103002-QFP160-P-2828B
ROMICE64
PX-ODB103S-O
CSIDE-MN10300
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MB91302A
Abstract: 32bit sdram
Text: New Products MB91302A FR Series 32-bit Microcontroller Mounted with SDRAM Controller MB91302A A microcontroller for built-in device controller using the 32-bit RISC CPU FR60 series. With its reinforced external bus interface and supporting DMAC flyby transfer,
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MB91302A
32-bit
MB91302A
MB91302A,
400Kbps)
FPT144PM12
32bit sdram
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rta2
Abstract: 1553B UT54ACTS220 UT69151
Text: 12.0 S MMIT LX/DX PIN IDENTIFICATION AND DESCRIPTION ADDRESS 15:0 CH DATA (15:0) CH CS MEMORY/ PROCESSOR INTERFACE 1553 INTERFACE CH RD/WR CH DMAR DMAG DMACK DTACK RRD UT69151 LX/DX TRS TC JTAG PORT JTAG RWR INTERRUPTS RCS TERAC ROMEN READY YF_INT SSYSF
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UT69151
rta2
1553B
UT54ACTS220
UT69151
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FFA000
Abstract: No abstract text available
Text: APPLICATION NOTE H8SX Family Ring Buffer Processing Using Extended Repeat Area Function of the DMAC Introduction The direct memory access controller DMAC performs ring buffer processing using the extended repeat area function. Target Device H8SX/1653 Contents
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H8SX/1653
REJ06B0623-0100/Rev
FFA000
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P132
Abstract: P133 P134 P150 M32176FnTFP renesas M32R sfr32176 M32176FnVFP
Text: APPLICATION NOTE 32176 Group Combination of Input Pin and DMAC 1. Overview The reference sample program combined input pin and DMAC for 32176 group appears on this document. 2. Introduction These application examples in this document are used in the following microcomputers and conditions.
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M32176FnVFP,
M32176FnTFP)
REJ05B0688-0100/Rev
P132
P133
P134
P150
M32176FnTFP
renesas M32R
sfr32176
M32176FnVFP
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SH7263
Abstract: 101C SH7203 iodefine CBR4800
Text: APPLICATION NOTE SH7263/SH7203 Group Data Transfer to On-chip Peripheral Modules with DMAC Introduction This application note provides an example of transferring data to on-chip peripheral modules with the direct memory access controller DMAC of the SH7263/SH7203.
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SH7263/SH7203
SH7263/SH7203.
SH7263/SH7203
REJ06B0734-0101/Rev
SH7263
101C
SH7203
iodefine
CBR4800
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A005
Abstract: SH7145
Text: APPLICATION NOTE SH7145 Group DMA in Single Address Mode Introduction This application note describes data transfer by the DMAC Direct Memory Access Controller module in single address mode. The DMAC performs high-speed data transfer in one bus cycle from external SRAM to an external
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SH7145
SH7145F
REJ06B0392-0100Z/Rev
A005
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101C
Abstract: 9600BPS
Text: APPLICATION NOTE SH7211 Group Data Transfer to On-chip Peripheral Modules with DMAC Introduction This application note provides an example of transferring data to on-chip peripheral modules with the direct memory access controller DMAC of the SH7211. Target Device
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SH7211
SH7211.
SH7211
REJ06B0725-0101/Rev
101C
9600BPS
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Untitled
Abstract: No abstract text available
Text: APPLICATION NOTE H8S Family SCI Continuous Transmission and Reception Introduction Transmits and receives 8-byte data between the H8S/2339 and H8/3687 in the clock synchronous mode. The DMAC is used. Target Device H8S/2339 Contents 1. Specifications . 2
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H8S/2339
H8/3687
H8S/2339
REJ06B0467-0100Z/Rev
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0C00
Abstract: 100C SH7286 SH7243
Text: APPLICATION NOTE SH7280 Group DMAC Dual Address Mode Introduction This application note provides an example of DMA transfer by means of the dual address mode of the direct memory access controller DMAC of the SH7285. Target Device SH7285 Contents 1. Preface. 2
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SH7280
SH7285.
SH7285
REJ06B0767-0100/Rev
0C00
100C
SH7286
SH7243
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A21E
Abstract: A18E Cs7e A17E
Text: APPLICATION NOTE H8S Family Data Transfer in the Single-Address Mode Introduction Uses the DMAC single-address mode to transfer data to an external device H8S/2215 . DMAC is started up at a falling edge of an external signal. Target Device H8S/2377 Contents
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H8S/2215)
H8S/2377
REJ06B0465-0100/Rev
A21E
A18E
Cs7e
A17E
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WE32100
Abstract: ALI m7 101b WE32104
Text: WE 32104 DMA Controller Description The WE 32104 DMA Controller DMAC is a mem ory-mapped peripheral device that performs memory-to-memory, memory fill, mem ory-to-peripheral, and peripheral-tomemory data transfers quickly and efficiently. The DMAC contains specialized hardware that
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32-bit
133-pin
225pF)
WE32100
ALI m7 101b
WE32104
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Untitled
Abstract: No abstract text available
Text: HD64180S-Network Processing Unit NPU The HD64180S network processing unit (NPU) contains a 2-channel high-speed, multifunction serial in terface, 8-bit CPU , 2-channel d irect memory access controller (DMAC) with a chained block transfer function, timers, etc., all integrated
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HD64180S---Network
HD64180S
FP-80A
CP-84
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sab80188
Abstract: SAB 8086 80188 siemens EM 235 cn
Text: 47E » • SIEMENS B235b05 GG313b4 T « S I E G SIEMENS AKTIENGESELLSCHAF High-lntegration SAB 80188/80188-1 8-Bit Microprocessor Preliminary SAB 80188 8 MHz • Integrated feature set - enhanced SAB 8088-2 CPU - clock generator - 2 independent high-speed DMAchannels
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B235b05
GG313b4
16-bit
T-49-17-07
fl235bOS
SAB80188
fi23SbDS
T-49-77-07
sab80188
SAB 8086
80188
siemens EM 235 cn
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Untitled
Abstract: No abstract text available
Text: Elan SC400 and ElanSC410 AMDÎ1 Single-Chip, Low-Power, PC/AT-Compatible Microcontrollers DISTINCTIVE CHARACTERISTICS Elan™SC400 and ElanSC410 Microcontrollers • ■ ■ Standard PC/AT system logic PICs, DMACs, timer, RTC - DOS, ROM-DOS, Windows, and industrystandard BIOS support
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SC400
ElanSC410
16550-compatible
16-038-BGA292-2
ES114
lanSC410
Am186,
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MB89351
Abstract: 3d450
Text: cP June 1990 Edition 1.0 FUJITSU DATA SHEET MB89351 SC SI Protocol Controller AC CHARACTERISTICS The Fujitsu MB89351 is a Small Computer System Interface SCSI Protocol Controller (SPC) specifically designed to implement a SCSI-bus to CPU/DMAC interface. Except for SCSI synchronous mode transfers, the MB89351 can handle virtually all
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MB89351
MB89351
16-bit
24-bit
the116)
64-LEAD
FPT-64P-M01)
3d450
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WE32104
Abstract: we32100 DMAC
Text: WE 32104 DMA Controller Description The WE 32104 DMA Controller DMAC is a memory-mapped peripheral device that performs memory-to-memory, memory fill, memory-to-peripheral, and peripheral-tomemory data transfers quickly and efficiently. The DMAC contains specialized hardware that
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32-bit
133-pin
225pF)
WE32104
we32100
DMAC
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MC6875
Abstract: f6800s F6844 EF6800 EF6844 EF68B44 6800 family DMA CB182
Text: THOMSON SEMICONDUCTORS MOS D IR E C T M E M O R Y ACCESS C O N TR O LLE R {DMAC The th e E F 6 8 4 4 D ire c t M e m o ry A ccess C o n tr o lle r D M A C ) p e rfo rm s f u n c tio n of tra n s fe rrin g data d ire c tly IN - C H A N N E L , S IL IC O N -G A T E )
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EF6844
CB-182
MC6875
f6800s
F6844
EF6800
EF68B44
6800 family DMA
CB182
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timing diagram of DMA Transfer
Abstract: No abstract text available
Text: NEC //P D 7 1 0 3 7 D irect M em ory Access C ontroller Description The H.PD71037 is a direct memory access controller DMAC for microprocessor systems which is faster and draws less power than its predecessors. The unit has four DMA channels, each having a 64K byte address area and
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uPD71037
PD8237A-5
PD71037C
M-PD71037GB-3B4
H-PD71037L
timing diagram of DMA Transfer
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