DM54LS12 Search Results

DM74LS12N

Abstract: DM74LS12 DM74LS12M DM54LS12J DM54LS12 DM54LS12W J14A M14A N14A W14B
Contextual Info: DM54LS12 DM74LS12 Triple 3-Input NAND Gates with Open-Collector Outputs General Description Pull-Up Resistor Equations This device contains three independent gates each of which performs the logic NAND function The open-collector outputs require external pull-up resistors for proper logical operation

54LS125

Abstract: 54LS125ADMQB 54LS125AFMQB 54LS125ALMQB DM54LS125AW DM74LS125AM DM74LS125AN E20A J14A
Contextual Info: NATIONAL SENICOND -CLOGIO 31E D bSGliaa QGbTöbB 3 54LS125A/DM54LS125A/DM74LS125A Quad TRI-STATE Buffers General Description that two outputs will attempt to take a common bus to oppo­ site logic levels, the disable time Is shorter than the enable time of the outputs.

54LS125

Abstract: 54LS125A 54LS125ADMQB 54LS125AFMQB 54LS125ALMQB DM54LS125A DM54LS125AJ DM54LS125AW DM74LS125A DM74LS125AM
Contextual Info: 54LS125A DM54LS125A DM74LS125A Quad TRI-STATE Buffers General Description This device contains four independent gates each of which performs a non-inverting buffer function The outputs have the TRI-STATE feature When enabled the outputs exhibit the low impedance characteristics of a standard LS output

DM54LS126AJ

Abstract: DM74LS126AM DM74LS126AN J14A M14A N14A
Contextual Info: DM54LS126A/DM74LS126A Quad TRI-STATE Buffers General Description output transistors are turned off presenting a high-impedance state to the bus line. Thus the output will act neither as a significant load nor as a driver. To minimize the possibility that two outputs will attempt to take a common bus to oppo­

DM74LS12N

Contextual Info: 2 National Semiconductor DM54LS12/DM74LS12 Triple 3-lnput NAND Gates with Open-Collector Outputs General Description Pull-Up Resistor Equations This device contains three independent gates each of which performs the logic NAND function. The open-collector out­

DM54LS122J

Abstract: DM74LS122M DM74LS122N J14A LS122 M14A N14A 74LS122 DM54LS122
Contextual Info: DM54LS122/DM74LS122 V*WM National Semiconductor Corporation DM54LS122/DM74LS122 Retriggerable One-Shot with Clear and Complementary Outputs General Description The DM54/74LS122 is a retriggerable monostable multivi­ brator featuring both positive and negative edge triggering

DM54LS123J

Abstract: DM74LS123N DM54 DM74LS123M J16A M16A N16A
Contextual Info: DM54LS123/DM74LS123 WjWJk National /Z /m Semiconductor Corporation DM54LS123/DM74LS123 Dual Retriggerable One-Shot with Clear and Complementary Outputs General Description The DM54/74LS123 is a dual retriggerable monostable mul­ tivibrator capable of generating output pulses from a few

DM54LS126AJ

Contextual Info: NATIONAL SEMICOND {LOGIC} fit. D e'H b S G l i a e □05t>3ci3 4 DM54LS126A/DM74LS126A Quad TRI-STATE Buffers output transistors are turned off presenting a high-impedance state to the bus line. Thus the output will act neither as a significant load nor as a driver. To minimize the possibility

DM74LS12N

Contextual Info: LS12 National Semiconductor DM54LS12/DM74LS12 Triple 3-Input NAND Gates with Open-Collector Outputs General Description Pull-Up Resistor Equations This device contains three independent gates each of which performs the logic NAND function. The open-collector out­

54LS125

Abstract: 54LS125ADMQB 54LS125AFMQB 54LS125ALMQB DM54LS125AJ DM54LS125AW DM74LS125AM DM74LS125AN E20A
Contextual Info: June 1989 54LS125A/DM54LS125A/DM74LS125A Quad TRI-STATE Buffers General Description This device contains lour independent gates each of which performs a non-inverting buffer function. The outputs have the TRI-STATE feature. When enabled, the outputs exhibit

54LS125ADMQB

Abstract: 54LS125AFMQB 54LS125ALMQB DM54LS125AW DM74LS125AM DM74LS125AN E20A J14A 54LS125
Contextual Info: LS125A a National Semiconductor 54LS125A/DM54LS125A/OM74LS125A Quad TRI-STATE Buffers General Description This device contains four independent gates each of which performs a non-inverting buffer function. The outputs have the TRI-STATE feature. When enabled, the outputs exhibit

ls125a

Contextual Info: LS125A National Semiconductor 54LS125A/DM54LS125A/DM74LS125A Quad TRI-STATE Buffers General Description that two outputs will attempt to take a common bus to oppo­ site logic levels, the disable time is shorter than the enable time of the outputs. This device contains four independent gates each of which

Contextual Info: N A T IO N A L -CL06IC3- S E H rC OND flb DE jjj b S Q U E E QDSbHfib 7 3 6501122 CO ' CM NATIONAL SEMICONDUCTOR D T r 5 ' / - / <? National Üj rt Semiconductor Corporation £ Q « N CO -I in £ Q 86D 5 6 38 6 DM54LS123/DM74LS123 Dual Retriggerable One-Shot with Clear and Complementary Outputs

74ls122 circuit applications

Abstract: 74LS122N DM9601 DM8601 74LS221 AN007 dm8602 54LS122J 54ls221 application circuits of ic 74121
Contextual Info: Fairchild Semiconductor Application Note 372 May 1984 INTRODUCTION Fairchild Semiconductor manufacturers a broad variety of industrial bipolar monostable multivibrators one-shots in TTL and LS-TTL technologies to meet the stringent needs of systems designers for applications in the areas of pulse generation, pulse shaping, time delay, demodulation, and edge detection of waveforms. Features of the various device types

DM74367

Abstract: 54175 71ls97 DM74109 DM8160 om541 ci 8602 gn block diagram 5401 DM transistor 74L10 74S136
Contextual Info: N ational Semiconductor Section 1 - 54/74 SSI DEVICES Connection Diagram s • Electrical Tables Section 2 - 54/74 M SI DEVICES Section 3 - National Semiconductor PROPRIETARY DEVICES Section 4 - National Semiconductor ADDITIONAL D EV KES t o NATIONAL Manufactured under one or more of the fo llowing U.S. patents: 3083262, 3189758, 3231797 , 3303356, 3317671, 3323071, 3381071, 3408542, 3421025, 3426423, 3440498, 3518750, 3519897, 3557431, 3560765,

Contextual Info: S E M IC O N D U C T O R tm DM74LS125A Quad 3-STATE Buffers General Description cant load nor as a driver. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the disable time is shorter than the enable time of the

U1221

Contextual Info: S E M IC O N D U C T O R tm DM74LS125A Quad 3-STATE Buffers This device contains fo u r independent gates each of which perform s a non-inverting buffer function. The outputs have the 3-STATE feature. W hen enabled, the outputs exhibit the low im pedance characteristics o f a standard LS output with

dm8601

Abstract: dm8602 74LS122N DM74LS122 74ls122 circuit applications 74LS123N 74121 application as pulse generator 74LS221 application circuits of ic 74121 LS 74121
Contextual Info: INTRODUCTION National Semiconductor manufacturers a broad variety of industrial bipolar monostable multivibrators one-shots in TTL and LS-TTL technologies to meet the stringent needs of systems designers for applications in the areas of pulse generation pulse shaping time delay demodulation and

IC CD4538

Abstract: PIN CONFIGURATION IC CD4047 CD4538 equivalent inverter circuit diagram using cd4047 IC CD4047 CD4538 applications CD4538 application note operation of IC CD4538 CD4538 application mm14538
Contextual Info: INTRODUCTION National Semiconductor manufactures a broad variety of industrial bipolar monostable multivibrators one-shots in TTL and LS-TTL technologies and MOS one-shots in CMOS and HCMOS technologies to meet the stringent needs of systems designers for applications in the areas of pulse generation pulse shaping time delay demodulation and edge

H9720

Abstract: m06g Marking Code SMD databook 937DMQB jm38510/10201bca 5962-8866207NA national semiconductor databook Motorola transistor smd marking codes DM54LS279J lm723
Contextual Info: N MILITARY / AEROSPACE DESIGN/PROCESS CHANGE NOTIFICATION PCN Nr: 1997 Listing GIDEP Nr: GIDEP Category: Issued: 01/21/97 TRB Nr: This is to advise you that a Design and/or Process Change will be made to the following MIL/AERO product s : Product ID (Description):

DM74LS125A

Abstract: DM54LS125AW DM74LS125AM DM74LS125AN 54LS125 54LS125ADMQB 54LS125AFMQB 54LS125ALMQB DM54LS125AJ
Contextual Info: DM74LS125A Quad 3-STATE Buffers General Description This device contains four independent gates each of which performs a non-inverting buffer function. The outputs have the 3-STATE feature. When enabled, the outputs exhibit the low impedance characteristics of a standard LS output with

c5088 transistor

Abstract: transistor C3207 TLO84CN sec c5088 IN5355B D2817A C3207 transistor toshiba f630 TLO81CP MC74HC533N
Contextual Info: Transistor - Diode Cross Reference - H.P. Part Numbers to JEDEC Numbers Part Num. 1820-0225 1820-0240 1820-0352 1820-1804 1821-0001 1821-0002 1821-0006 1850-0062 1850-0064 1850-0075 1850-0076 1850-0093 1850-0099 1850-0126 1850-0137 1850-0150 1850-0151 1850-0154

JX - 638

Abstract: 54LS125A
Contextual Info: June 1989 5 4 L S 12 5A /D M 5 4L S 12 5A /D M 74 L S 1 25 A Quad TR I-STA TE B uffers General Description This device contains four independent gates each of which performs a non-inverting buffer function. The outputs have the TRI-STATE feature. When enabled, the outputs exhibit

54LS125

Abstract: 54LS125ADMQB 54LS125AFMQB 54LS125ALMQB DM54LS125AJ DM54LS125AW DM74LS125A DM74LS125AM DM74LS125AN E20A
Contextual Info: S E M IC O N D U C T O R tm DM74LS125A Quad 3-STATE Buffers cant load nor as a driver. To m inim ize th e possibility th a t two outputs will attem pt to ta ke a com m on bus to opposite logic levels, th e disable tim e is shorter than the enable tim e of the