DHBD Search Results

9718h

Abstract: 11973H VC12 LEVEL ONE COMMUNICATIONS SXT6051 SXT framer HT 648 Decoder Rx 9802h
Contextual Info: DATA SHEET MAY 1998 Revision 1.1 SXT6051 STM-1/0 SDH Overhead Terminator General Description Features The SXT6051 Overhead Terminator implements the Regenerator Section Termination, Multiplexer Section Termination and Higher Order Path Termination in STM-0

Contextual Info: Datasheet JUNE 1999 Revision 2.0 LXT6051 STM-170 SDH Overhead Terminator General Description The LXT6051 Overhead Terminator implements the Regenerator Section Termination, Multiplexer Section Termination and Higher Order Path Termination in STM-0 51Mb/s and STM-1 (155Mb/s) multiplexers. It provides

VME bus controller

Abstract: VME DAISY CHAIN dhbd E1200 VME1200 VME controller single bus master CPU DSP
Contextual Info: Ä X -* V M E 1200 VMEbus Master Controller with System Arbiter T • C H M O L November 1988 Distinctive Features. Applications_ • • Two device chip set contains: - Bus requester - Single level system arbiter - VMEbus controller

VME DAISY CHAIN

Contextual Info: VME 1210/20 Slot 1 and Non-Slot 1 VMEbus Master Controllers March 1989 Applications-* VMEbus masters residing in slot 1 boards VME 1210 * VMEbus masters residing in non-slot 1 boards (VME 1220) Distinctive Features_

Contextual Info: SONY C X P 1 0 2 1 Q System Controller for Compact Disc Players Description The CXP1021Q is a 4-bit single chip microcomputer based on the SPC500 series. It incorporates programs in firmware for CD operations. It can be connected directly to the CDL-40 series of LSIs for

AD401

Contextual Info: Dec e ,'990 RECEIVED ANALOG DEVICES A U G 'j U is a u RS-232, RS-422 Low Power Drivers/Receivers ¿CVv' & ethnical Information III#AD401 /ÀD40 r j ^ SaSS FEATURES RS-232 and RS-422 on One Chip Loopback for Self-testing Mode Selectable Short Circuit Protection

ABBA

Abstract: LXT6051QE 9922H AU-AIS LXT6051 VC12 SLXT6051 LXT6251 W117
Contextual Info: Datasheet JUNE 1999 Revision 2.0 LXT6051 STM-1/0 SDH Overhead Terminator General Description Features The LXT6051 Overhead Terminator implements the Regenerator Section Termination, Multiplexer Section Termination and Higher Order Path Termination in STM-0

Contextual Info: VM E1200 t% c h m o l o o v ^ VMEbus Master Controller with System Arbiter November 1988 Applications. Distinctive Features. • VMEbus master and system controller residing in slot 1 • Other VMEbus masters (residing in other slots) Two device chip set contains:

KS0066F00

Contextual Info: CMOS DIGITAL INTEGRATED CIRCUIT KS0066 DOT MATRIX LCD CONTROLLER & DRIVER The KS0066 is a dot matrix LCD driver & controller LSI which is fabricated by low power CMOS technology. FUNCTION • Character type dot matrix LCD driver & controller • Internal driver: 16 common and 40 segment signal output.

Contextual Info: VME 1210/1220 A 3 L May 1989 Slot 1 and Non-Slot 1 VMEbus Master Controllers Distinctive Features_ • VME 1210 provides two device chip set for slot 1 master bus controller and single level arbiter Applications_

LXT6282

Abstract: DTD17 MTC11 MTC15 header 3x2 LXT6251A intel C96 74HC04 LXT344 25X2
Contextual Info: POWER.SCH POWER SUPPLIES MHICLK MHICLK J3 EXTCLKA EXTCLKA MHBCLK MHBCLK BNC-4 LXT6051.SCH J4 EXTCLKB MRESET EXTCLKB ALTSOH.sch BNC-4 MRESET MRESET J5 EXTCLKC MRESET EXTCLKC TSYNCCLKM TSYNCCLKM BNC-4 FPGA FOR SERIAL ACCESS TSYNCCLKM LXT6051A ORDERWIR.SCH TROWM

VME bus controller

Abstract: PLD VME VME bus arbitration 1210a vme bus specification 1210B vme case 1210 LCC
Contextual Info: VME 1210/20 Slot 1 and Non-Slot 1 VMEbus Master Controllers March 1989 Distinctive Features. * VME 1210 provides two device chip set for slot 1 master bus controller and single level arbiter * VME 1220 provides two device chip set for non-slot 1 master bus controller

Contextual Info: Product Overvic FEBRUARY 1998 Revision 7.0 SXT6051 STM-1/0 SDH Overhead Terminator General Description Features The SXT6051 Overhead Terminator implements the Regenerator Section Termination, Multiplexer Section Termination and Higher Order Path Termination in STM-0

LXT6282

Abstract: JP15 adpll intel pdh e2 74AC04 motorola LXT6251A quad 74HC04 NOT GATE datasheet STM-1 JP16 LXT334
Contextual Info: LDB6x51 Evaluation Board for LXT6051, LXT6251A, and LXT6282 Developer Manual January 2001 As of January 15, 2001, this document replaces the Level One document LDB6x51 Evaluation Board for LXT6051, LXT6251, and LXT6282 User Guide. Order Number: 249305-001

Contextual Info: WAY 1 0 JSJ3 VME 1210/1220 June 1990 Slot 1 and Non-Slot 1 VMEbus Master Controllers Distinctive Features_ • VME 1210 provides two device chip set for slot 1 master bus controller and single level arbiter • VME 1220 provides two device chip set for non-slot 1

Contextual Info: T H I S DRAWING I S UNPUBLI SHED. C RELEASED FOR PU B L I C A T I O N COPYRIGHT 2000 1I AAA J L L 2000 LOC ALL RI GHTS RESERVED. AJ l WI AL LA T AZ_ RAD I U A M AU AU I IU I L MAI DX I I A A IA UA J / iL ( \ 2 FOR A P P C I C A T I ON INFORMATION 3 FOR PERFORMANCE