DG2S733 Search Results

Contextual Info: TOSHIBA U C /U P b4E D «^724^ TOSHIBA DG2S733 bBT TMP90C840A/841 A The bus operation in the general purpose interrupt processing and the micro DMA processing is shown in “Table 1.4 (2) Bus Operation for Executing Instructions” in the previous section.

Contextual Info: b4E D TOSHIBA UC/UP ^724^ DQ2S731 flbb TO SH IB A TM P90C840A/841A FFOOH+V + O : Number of transfer FFOOH+V+1 : Destination address (Lower) FF00H +V + 2 : Destination address (Upper) FF00H + V + 3 : Source address (Lower) FFOOH + V + 4 : Source address (Upper)