DFLIPFLOP Search Results

vq80

Abstract: A40MX02 one time
Contextual Info: Revision 3 40MX and 42MX Automotive FPGA Families Features High Capacity Ease of Integration • Single-Chip Applications ASIC Alternative for Automotive • Up to 100% Resource Utilization and 100% Pin Locking • 3,000 to 54,000 System Gates • Deterministic, User-Controllable Timing

antifuse programming technology

Abstract: 40MX 42MX A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36 42MX24
Contextual Info: v6.0 40MX and 42MX FPGA Families Fe a t ur es High C apaci t y • • • • • • Commercial, Military Temperature, and MIL-STD-883 Ceramic Packages Single-Chip ASIC Alternative 3,000 to 54,000 System Gates Up to 2.5 kbits Configurable Dual-Port SRAM

high voltage current mirror

Abstract: RBS 2401 HIP5600 HIP5500 IRF450 transistor 1n4000 sERIES DIODES "high voltage current mirror" Automatic voltage regulator RBS irf450 mosfet drive circuit diagram HIP2500
Contextual Info: TM No. AN9335 Intersil Intelligent Power December 1993 HIP5500 HIGH VOLTAGE 500VDC POWER SUPPLY DRIVER IC Author: George E. Danz Introduction (shown shaded in Figure 1), this approach lacks the advantages of a “distributed” turn-off device and doesn’t bypass

SIGNAL PATH designer

Abstract: 32r510
Contextual Info: cémiMÍatis SSI 32P546 Read Data Processor with Pulse Slimming June, 1989 DESCRIPTION FEATURES The SSI 32P546 is a bipolar integrated circuit that provides all data processing necessary for detection and qualification of M FM or RLL encoded read signals.

RT3PE600L

Abstract: RT3PE3000L AES-128 PAC10 LG484 ProASICPLUS Flash Family FPGAs Advanced v0.1
Contextual Info: Advance v0.1 Radiation-Tolerant ProASIC3 Low-Power SpaceFlight Flash FPGAs with Flash*Freeze Technology Features and Benefits • High-Performance, Low-Skew Global Network • Architecture Supports Ultra-High Utilization MIL-STD-883 Class B Qualified Packaging

32P541

Abstract: 32P541-CH SSI32P541 SSI 32P541 32p541-cl Signal Path Designer ssi32p54
Contextual Info: SSI 32P541 Read Data Processor ¿émMskms February, 1990 DESCRIPTION FEATURES The SSI 32P541 is a bipolar integrated circuit that provides all data processing necessary lor detection and qualification of MFM or RLL encoded read signals. The circuit will handle data rates up to 15 Mbit/s.

ACTEL FUSION AFS1500

Abstract: FlashPro3 PQ208 QN108 QN180 M1AFS1500 AFS250 rc oscillator M-LVDS
Contextual Info: Preliminary v1.7 Actel Fusion Mixed-Signal FPGAs Family with Optional ARM® Support Features and Benefits – Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz Low Power Consumption High-Performance Reprogrammable Flash Technology • • • • • Single 3.3 V Power Supply with On-Chip 1.5 V Regulator

Advanced Boot Block Flash

Abstract: AES-128 CS201 CS281 CS289 AGLP125
Contextual Info: v1.5 IGLOO PLUS Low-Power Flash FPGAs with Flash*Freeze Technology Features and Benefits Low Power • • • • • 1.2 V to 1.5 V Core Voltage Support for Low Power Supports Single-Voltage System Operation 5 µW Power Consumption in Flash*Freeze Mode

A3P600

Abstract: A3P060 A3P1000 A3P125 A3P250 AECQ100 AEC-Q100 FG144 FG256 FG484
Contextual Info: v1.0 Automotive ProASIC3 Flash Family FPGAs Features and Benefits Low Power • 1.5 V Core Voltage • Support for 1.5-V-Only Systems • Low-Impedance Flash Switches High-Temperature AEC-Q100–Qualified Devices • Grade 2 105°C TA 115°C TJ • Grade 1 125°C TA (135°C TJ)

A3PE3000L FG484

Abstract: Actel pdf on radio emitter A3PE3000L FG144 FG256 FG324 FG484 PQ208 TDP 245 Y
Contextual Info: v1.3 ProASIC3L Low-Power Flash FPGAs with Flash*Freeze Technology Features and Benefits Low Power • Dramatic Reduction in Dynamic and Static Power Savings • 1.2 V to 1.5 V Core and I/O Voltage Support for Low Power • Low Power Consumption in Flash*Freeze Mode Allows for

QN68

Abstract: VQ100 actel part markings
Contextual Info: Advance v0.4 ProASIC®3 nano Flash FPGAs Features and Benefits Advanced I/Os Wide Range of Features • 10 k to 250 k System Gates • Up to 36 kbits of True Dual-Port SRAM • Up to 71 User I/Os Reprogrammable Flash Technology • • • • 130-nm, 7-Layer Metal 6 Copper , Flash-Based CMOS Process

CORE8051

Abstract: FlashPro3 AES-128 FG256 PQ208 ac motor variable speed control rc oscillator
Contextual Info: Preliminary v0.4 Actel Fusion Mixed-Signal FPGA for the MicroBlade Advanced Mezzanine Card Solution Features and Benefits • Targeted to Advanced Mezzanine Card AdvancedMC Designs • Designed in Partnership with MicroBlade • 8051-Based Module Management Controller (MMC)

GTL33

Abstract: CAT16-LV4F12 PAC10 JESD8-12A
Contextual Info: 2 – IGLOOe DC and Switching Characteristics General Specifications DC and switching characteristics for –F speed grade targets are based only on simulation. The characteristics provided for the –F speed grade are subject to change after establishing FPGA

RT3PE3000L

Abstract: RT3PE600L LG484 AES-128 ieee 1532 ProASIC3
Contextual Info: Advance v0.1 Radiation-Tolerant ProASIC3 Low-Power SpaceFlight Flash FPGAs with Flash*Freeze Technology Features and Benefits • High-Performance, Low-Skew Global Network • Architecture Supports Ultra-High Utilization MIL-STD-883 Class B Qualified Packaging

Contextual Info: Revision 22 IGLOO Low Power Flash FPGAs with Flash*Freeze Technology Features and Benefits Low Power • • • • • 1.2 V to 1.5 V Core Voltage Support for Low Power Supports Single-Voltage System Operation 5 µW Power Consumption in Flash*Freeze Mode

Contextual Info: IDT54/74FCT163652/A/C PRODUCT PREVIEW 3.3V CMOS 16-BIT BUS TRANSCEIVER/ REGISTERS Integrated Device Technology, Inc. FEATURES: • 0.5 MICRON CMOS Technology • Typical tsK o (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)

Contextual Info: FAST CMOS 16-BIT BUS IDT54/74FCT16652T/AT/CT/ET IDT54/74FCT162652T/AT/CT/ET TRANSCEIVER/ REGISTERS In te g ra te d D ev ice T e c h n o lo g y , Inc. FEATURES: vices are organized as two independent 8-bit bus transceivers with 3-state D-type registers. For example, the xOEAB and

tl072 spice

Abstract: D1N4007 QBC547B BF245B spice bf245b spice model inverter using irfz44n 2N5171 SPICE diode 1N750 LTspice 50HZ oscillator sinus vco
Contextual Info: SPICE-SchaltungsSimulation mit LTspice IV Tutorial zum erfolgreichen Umgang mit der frei im Internet www.linear.com erhältlichen SPICEVollversion der Firma Linear Technologies Tutorial-Version 2.2 Copyright by Gunthard Kraus, Oberstudienrat i.R. an der Elektronikschule Tettnang

CAT16-LV4F12

Abstract: PAC10 RAM512X18
Contextual Info: 2 – ProASIC3E DC and Switching Characteristics General Specifications DC and switching characteristics for –F speed grade targets are based only on simulation. The characteristics provided for the –F speed grade are subject to change after establishing FPGA

QN68

Abstract: VQ100 PAC11 ProASIC3 handbook
Contextual Info: Advance v0.5 ProASIC®3 nano Flash FPGAs Features and Benefits Advanced I/Os Wide Range of Features • 10 k to 250 k System Gates • Up to 36 kbits of True Dual-Port SRAM • Up to 71 User I/Os Reprogrammable Flash Technology • • • • 130-nm, 7-Layer Metal 6 Copper , Flash-Based CMOS Process

AES-128

Abstract: FG256 FG484
Contextual Info: v2.0 IGLOOe Low-Power Flash FPGAs with Flash*Freeze Technology Features and Benefits Low Power • • • • 1.2 V to 1.5 V Core Voltage Support for Low Power Supports Single-Voltage System Operation Low-Power Active FPGA Operation Flash*Freeze Technology Enables Ultra-Low Power

A54 ZENER

Abstract: AFS600-FG256 mark AT0 QN108 CORE8051 bipolar ROM
Contextual Info: v2.0 Actel Fusion Family of Mixed-Signal FPGAs Features and Benefits In-System Programming ISP and Security High-Performance Reprogrammable Flash Technology Advanced Digital I/O • • • • • Secure ISP with 128-Bit AES via JTAG • FlashLock® to Secure FPGA Contents

ABT16652

Contextual Info: FAST CMOS 16-BIT BUS IDT54/74FCT16652T/AT/CT/ET IDT54/74FCT162652T/AT/CT/ET TRANSCEIVER/ REGISTERS Integrated Device Technology, Inc. FEATURES: • Common features: – 0.5 MICRON CMOS Technology – High-speed, low-power CMOS replacement for ABT functions

Contextual Info: heulett - packard/ cupnts b lE D • 4447564 0000=135 SSfl ■ H P A What H E W L E T T mL'HMP A C K A R D Decision Circuit Comparator/D-FF Technical Data HDMP-2003 HDMP-2004 F eatures FIBER OPTICS • Silicon B ipolar T echnology • ECL L evels • O perational to 1.5 GBit Input