DCL2 Search Results

ZD-01674

Contextual Info: ZY8160 60A DC-DC Intelligent POL 8V to 14V Input • 0.5V to 2.75V Output Data Sheet Member of the Applications • Low voltage, high density systems with Intermediate Bus Architectures IBA • Point-of-load regulators for high performance DSP, FPGA, ASIC, and microprocessors

PEB 20570

Abstract: H1442 DCL2000 various 4 mhz crystal osc PEB 20571
Contextual Info: Addendum DS2.1, 2003-08-04 DELIC-LC/DELIC-PB DSP Embedded Line and Port Interface Controller PEB 20570/PEB 20571/PEF 20570/PEF 20571 Version 3.1 1 Addendum to “DELIC Clock System Synchronization” The DELIC Clock System Synchronization is described in the DELIC-LC PEB 20570/

TB 1226 BN

Abstract: TB 1226 EN ICF CP 1005 DAC ic 0808 pin diagram bosch edc 16, component protection TB 1275 N DATA SHEET 6R 738 CHN 623 Diodes chn 850 CHN 703
Contextual Info: REJ09B0320-0200 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. SH7261Group 32 Hardware Manual TM

HD61830A00

Abstract: hd61830B00 LCD Controller HD61830 HD61830 HD6303 HM6116 HD61830B HD61830B00H marking db2 V6 marking code diode
Contextual Info: To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog

siemens 6XV1-830-0AH10

Abstract: clifton resolver thermocouple type K krupp PIC900 A52 opto sensor inductosyn 11brw-300 Siemens 9-pin sub-D pinout RD2 earth leakage relay Balluff absolute encoder
Contextual Info: PiC900 Hardware Manual Version 13.0 Giddings & Lewis Controls, Measurement and Sensing NOTE Progress is an ongoing commitment at Giddings & Lewis. We continually strive to offer the most advanced products in the industry; therefore, information in this document is subject to change without

Upn scrambler

Abstract: C165 C166 PEB20570 80386EX 128x8 ram ALCATEL PBX intel 4040 PEB 4165 T PEB22521
Contextual Info: ICs for Communications DSP Embedded Line and Port Interface Controller DELIC-LC PEB 20570 Version 2.3 DELIC-PB PEB 20571 Version 2.3 Preliminary Data Sheet 02.00 DS 2 PEB 20570 PEB 20571 Revision History: Current Version: 02.00 Previous Version: - Page Page

ELCB 3 phase CONNECTION DIAGRAM

Abstract: ELCB CONNECTION DIAGRAM
Contextual Info: Transistor Inverter Built-in EMI noise filter Introducing the world’s top class compact inverter To users of our inverters : Our inverters are designed to control the speeds of three-phase induction motors for general industry. ！ Precautions * Read the instruction manual before installing or operating the inverter unit and store it in a safe place for reference.

stk403-120

Abstract: ZY7120 VS-22 SR-332 ZM00056-KIT ZD001
Contextual Info: ZY7120 20A DC-DC Intelligent POL Data Sheet 3V to 13.2V Input • 0.5V to 5.5V Output Member of the Applications • Low voltage, high density systems with Intermediate Bus Architectures IBA • Point-of-load regulators for high performance DSP, FPGA, ASIC, and microprocessor applications

ZM00056-KIT

Abstract: ZY8105
Contextual Info: ZY8105 5A DC-DC Intelligent POL 8V to 14V Input • 0.5V to 5.5V Output Preliminary Data Sheet Member of the Applications • Low voltage, high density systems with Intermediate Bus Architectures IBA • Point-of-load regulators for high performance DSP, FPGA, ASIC, and microprocessors

Contextual Info: ZY7115 15A DC-DC Intelligent POL Data Sheet 3V to 13.2V Input • 0.5V to 5.5V Output Member of the Applications • Low voltage, high density systems with Intermediate Bus Architectures IBA • Point-of-load regulators for high performance DSP, FPGA, ASIC, and microprocessor applications

fah 15 fuse

Contextual Info: ZY8120 20A DC-DC Intelligent POL 8V to 14V Input • 0.5V to 5.5V Output Data Sheet Member of the Applications • Low voltage, high density systems with Intermediate Bus Architectures IBA • Point-of-load regulators for high performance DSP, FPGA, ASIC, and microprocessors

Contextual Info: ZY8160 60A DC-DC Intelligent POL 8V to 14V Input • 0.5V to 2.75V Output Data Sheet Member of the Applications  Low voltage, high density systems with Intermediate Bus Architectures IBA  Point-of-load regulators for high performance DSP, FPGA, ASIC, and microprocessors

Contextual Info: ZY7007 7A DC-DC Intelligent POL Preliminary Data Sheet 3V to 13.2V Input • 0.5V to 5.5V Output Member of the Applications • Low voltage, high density systems with Intermediate Bus Architectures IBA • Point-of-load regulators for high performance DSP,

Contextual Info: ZY8140 40A DC-DC Intelligent POL 8V to 14V Input • 0.5V to 3.65V Output Preliminary Data Sheet Member of the Applications • Low voltage, high density systems with Intermediate Bus Architectures IBA • Point-of-load regulators for high performance DSP, FPGA, ASIC, and microprocessors

Contextual Info: ZY7010L 10A DC-DC Intelligent POL Data Sheet 3V to 13.2V Input • 0.5V to 5.5V Output Member of the Applications • Low voltage, high density systems with Intermediate Bus Architectures IBA • Point-of-load regulators for high performance DSP, FPGA, ASIC, and microprocessor applications

Contextual Info: ZY7007 7A DC-DC Intelligent POL Data Sheet 3V to 13.2V Input • 0.5V to 5.5V Output Member of the Applications • Low voltage, high density systems with Intermediate Bus Architectures IBA • Point-of-load regulators for high performance DSP, FPGA, ASIC, and microprocessor applications

Contextual Info: ZY7010L 10A DC-DC Intelligent POL Data Sheet 3V to 13.2V Input • 0.5V to 5.5V Output Member of the Applications • Low voltage, high density systems with Intermediate Bus Architectures IBA • Point-of-load regulators for high performance DSP, FPGA, ASIC, and microprocessor applications

Contextual Info: ZY8110 10A DC-DC Intelligent POL 8V to 14V Input • 0.5V to 5.5V Output Data Sheet Member of the Applications  Low voltage, high density systems with Intermediate Bus Architectures IBA  Point-of-load regulators for high performance DSP, FPGA, ASIC, and microprocessors

Contextual Info: ZY8120 20A DC-DC Intelligent POL 8V to 14V Input • 0.5V to 5.5V Output Data Sheet Member of the Applications • Low voltage, high density systems with Intermediate Bus Architectures IBA • Point-of-load regulators for high performance DSP, FPGA, ASIC, and microprocessors

Contextual Info: ZY7015 15A DC-DC Intelligent POL Data Sheet 3V to 13.2V Input • 0.5V to 5.5V Output Member of the Applications • Low voltage, high density systems with Intermediate Bus Architectures IBA • Point-of-load regulators for high performance DSP, FPGA, ASIC, and microprocessor applications

Contextual Info: ZY7007 7A DC-DC Intelligent POL Data Sheet 3V to 14V Input • 0.5V to 5.5V Output Member of the Applications  Low voltage, high density systems with Intermediate Bus Architectures IBA  Point-of-load regulators for high performance DSP, FPGA, ASIC, and microprocessor applications

Contextual Info: DATA SHEET DP7120G 20A DC-DC Intelligent dPOL • Input voltage range: 8V–14V • Output voltage range: 0.7V–5.5V at 0 - 20A.  Programmable dynamic output voltage positioning for better load transient response  Choice of 500KHz switching for highest efficiency or 1MHz for lowest

IAD V2.3

Abstract: DELIC-PB Software Users Manual iomu allegro micro DELIC-LC
Contextual Info: D E L I C - P B S o f t w a r e U se r’ s M an u a l , D S 1 , N o v . 2 00 0 DELIC-PB DSP Embedded Line and Port Interface Controller PEB 20571 Version 2.3 Wi r ed Communications N e v e r s t o p t h i n k i n g . Edition 2000-11-21 Published by Infineon Technologies AG,

dcl1

Contextual Info: fÆIK INTNTL MICROELCTN DCL Digital Cell Library IMP’s Digital Cell Library DCL is designed to be compatible with IMP’s Analog Cell Library (ACL). The dual layer metal, silicon gate CMOS Standard Cells offer high performance with low power consumption