A8904SLBTR-T
Abstract: D2627 A8902 A8902-A A8902CLBA A8904 A8904SLP MS-013 3 phase dynamic braking for forward and reverse direction of 3 phase motor
Text: A8904 3-Phase Brushless DC Motor Controller/Driver with Back EMF Sensing Discontinued Product These parts are no longer in production The device should not be purchased for new design applications. Samples are no longer available. Date of status change: November 1, 2010
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A8904
A8904SLBTR-T
D2627
A8902
A8902-A
A8902CLBA
A8904
A8904SLP
MS-013
3 phase dynamic braking for forward and reverse direction of 3 phase motor
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SSTUA32864
Abstract: SSTUA32866
Text: SSTUG32868 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applications Rev. 01 — 23 April 2007 Product data sheet 1. General description The SSTUG32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank
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SSTUG32868
28-bit
SSTUG32868
14-bit
SSTUA32864
SSTUA32866
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Untitled
Abstract: No abstract text available
Text: PRELIMINARY DRAM MT4LC4M16F5 FEATURES PIN ASSIGNMENT Top View • Single +3.3V +0.3V p ow er sup ply • Industry-standard x l6 pinout, tim ing, functions and packages • 12 ro w , 10 colum n addresses • High-perform ance C M O S silicon-gate process
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MT4LC4M16F5
096-cycle
50-Pin
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TCD2713DG
Abstract: Toshiba
Text: TCD2713DG TOSHIBA CCD Linear Image Sensor TENTATIVE CCD Charge Coupled Device TCD2713DG The TCD2713DG is a high sensitive and low dark current 7500 pixels x 4 line CCD color image sensor. The sensor is designed for color scanner. The device contains a row of 7500 pixels × 4 line photodiodes
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TCD2713DG
TCD2713DG
Toshiba
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DDR2-800
Abstract: SSTUA32864 SSTUA32866 E6G3
Text: SSTUM32868 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications Rev. 02 — 2 March 2007 Product data sheet 1. General description The SSTUM32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank
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SSTUM32868
28-bit
DDR2-800
SSTUM32868
14-bit
SSTUA32864
SSTUA32866
E6G3
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AD364
Abstract: AD363 AD363RK AD363RKD AD363RS AD363RSD Analog
Text: ANALOG ► DEVICES FEATURES Complete 16-Channel, 12-Bit Data Acquisition Systems AD363/AD364 AD363 FUNCTIONAL BLOCK DIAGRAM DC POWER tISV, +5V AD363 16-Channel Data Acquisition Input Stage w ith : Digitally Controlled Channel Selection/M ode Control 16 Single-Ended or 8 Differential Channels
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16-Channel,
12-Bit
AD363/A0364
AD363
16-Channel
AD364
AD363
AD364
AD363RK
AD363RKD
AD363RS
AD363RSD
Analog
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Untitled
Abstract: No abstract text available
Text: PRELIMINARY M IC R O N • 4 MEG X 16 FPM DRAM TECHNOLOGY. INC DRAM MT4LC4M16F5 FEATURES • Single +3.3V ±0.3V power supply • Industry-standard xl6 pinout, timing, functions and packages • 12 row, 10 column addresses • High-performance CMOS silicon-gate process
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MT4LC4M16F5
096-cycle
50-Pin
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J2 Q24A B
Abstract: Q24A ICS98ULPA877A ICSSSTUAF32868B IDTCSPUA877A q9bq12b
Text: DATASHEET 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description QERR pin active low . The convention is even parity, i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. To calculate parity, all DIMM-independent D-inputs
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28-BIT
enters284
199707558G
J2 Q24A B
Q24A
ICS98ULPA877A
ICSSSTUAF32868B
IDTCSPUA877A
q9bq12b
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MSM27C3255CZ
Abstract: 70pin-SSOP
Text: ¡ Semiconductor 1A MSM27C3255CZ 1,048,576-Double Word x 32-Bit or 2,097,152-Word x 16-Bit 4-Double Word x 32-Bit or 8-Word x 16-Bit Page Mode One Time PROM DESCRIPTION The MSM27C3255CZ is a 32Mbit electrically Programmable Read-Only Memory with page mode.
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MSM27C3255CZ
576-Double
32-Bit
152-Word
16-Bit
16-Bit
MSM27C3255CZ
32Mbit
32bit
70pin-SSOP
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70038
Abstract: No abstract text available
Text: Tem ic DG201HS Semiconductors High-Speed Quad SPST CMOS Analog Switch Features Benefits Applications • • • • • • • • • • • • • • • • • • • • • • • Fast Switching— toN: 38 ns Low On-Resistance: 25 £2 Low Leakage: 100 pA
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DG201HS
HI201HS,
ADG201HS
DG201HS
70038
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KU80486SX
Abstract: 240486 KU80486SXSA33 ku80486 272769 240950 A80486SXSA33 SL ENHANCED I486 D1542 a80486sx
Text: Embedded Intel486 SX Processor Datasheet Product Features • ■ ■ ■ ■ 32-Bit RISC Technology Core 8-Kbyte Write-Through Cache Four Internal Write Buffers Burst Bus Cycles Dynamic Bus Sizing for 8- and 16-bit Data Bus Devices SL Technology ■ ■
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Intel486TM
32-Bit
16-bit
196-Lead
168-Pin
64-Bit
KU80486SX
240486
KU80486SXSA33
ku80486
272769
240950
A80486SXSA33
SL ENHANCED I486
D1542
a80486sx
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Untitled
Abstract: No abstract text available
Text: Ordering number : ENN6867 CMOS IC LC75343M Electronic Volume Control System on-Chip Overview Package Dimensions unit: mm 3263-MFP36SDJ 375 mil 15.2 [LC75343M] 19 0.65 7.9 36 10.5 • Volume: 0 dB to –78 dB (1-dB step) and –∞ (64 positions) 0 dB to –50 dB (1-dB step), –50 dB to –70 dB
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ENN6867
LC75343M
3263-MFP36SDJ
LC75343M]
70-dB
10-dB
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MSM27V1655CZ
Abstract: No abstract text available
Text: ¡ Semiconductor 1A MSM27V1655CZ 524,288-Double Word x 32-Bit or 1,048,576-Word x 16-Bit 4-Double Word x 32-Bit or 8-Word x 16-Bit Page Mode One Time PROM DESCRIPTION The MSM27V1655CZ is a 16Mbit electrically Programmable Read-Only Memory with page mode. Its
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MSM27V1655CZ
288-Double
32-Bit
576-Word
16-Bit
16-Bit
MSM27V1655CZ
16Mbit
32bit
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Untitled
Abstract: No abstract text available
Text: MX2303222 32M-BIT MASK ROM 16/32-BIT OUTPUT FEATURES ORDER INFORMATION • Bit organization - 2M x 16 (word mode) - 1 M x 32 (double word mode) • Fast access time - Random access: 100ns (max. - Page access: 30ns (max.) • Page - 8 double words per page
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MX2303222
32M-BIT
16/32-BIT
100ns
100mA
500mil)
MX23C3222MC-10
100ns
MX23C3222MC-12
120ns
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Untitled
Abstract: No abstract text available
Text: WEDPS512K32V-XBX 512Kx32 SRAM 3.3V MULTI-CHIP PACKAGE ADVANCED* FEATURES n Low Power CMOS n Access Times of 12, 15, 17, 20ns n TTL Compatible Inputs and Outputs n Fully Static Operation: n Packaging • 143 PBGA, 16mm x 18mm, 288mm 2 • No clock or refresh required.
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WEDPS512K32V-XBX
512Kx32
288mm
512Kx32;
1Mx16
WEDPS512K32V-XBX
512Kx32
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74138 decoder
Abstract: pin diagram of ic 74138 IC 3-8 decoder 74138 pin diagram application of IC 74138 ic 74138 pin diagram
Text: AEPSD1M32 STATIC RAM MODULE July 7, 1992 ^ ADVANCED ELECTRONIC PKG 5 0 IE D • 0254713 000031=1 4 1 1 * A E P > > 1,048,576 x 32 Organization > > On Board Buffers for All Address Lines and Control Lines > > Double Sided to Maximum Bit Density > > High Speed Access Time
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AEPSD1M32
AEPSD1M32
74138 decoder
pin diagram of ic 74138
IC 3-8 decoder 74138 pin diagram
application of IC 74138
ic 74138 pin diagram
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smd code D35
Abstract: LQFP048-P0707 1a6h CXA2006Q CXD1267AN CXD2311AR CXD2452R ICX098AK 11VSS3
Text: CXD2452R Timing Generator for Progressive Scan CCD Image Sensor Description The CXD2452R is a timing generator which generates the timing pulses for performing progressive scan readout for digital still cameras and personal computer image input applications using the
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CXD2452R
CXD2452R
ICX098AK
2340fH
1170fH,
780fH
48PIN
LQFP-48P-L01
LQFP048-P-0707
smd code D35
LQFP048-P0707
1a6h
CXA2006Q
CXD1267AN
CXD2311AR
11VSS3
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INTELDX4 write-through
Abstract: 242202
Text: in t e i EMBEDDED WRITE-BACK ENHANCED lntelDX4 PROCESSOR Up to 100 MHz Operation Data Bus Parity Generation and Checking Integrated Floating-Point Unit Speed-Multiplying Technology Boundary Scan JTAG 32-Bit RISC Technology Core 3.3-Volt Processor, 75 MHz, 25 MHz
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32-Bit
208-Lead
16-Kbyte
168-Pin
16-bit
32-BH
INTELDX4 write-through
242202
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Untitled
Abstract: No abstract text available
Text: TMS320C30 DIGITAL SIGNAL PROCESSOR SPRS032A – APRIL 1996 – REVISED JUNE 1997 D D D D D D D High-Performance Floating-Point Digital Signal Processor DSP – TMS320C30-50 (5 V) 40-ns Instruction Cycle Time 275 MOPS, 50 MFLOPS, 25 MIPS – TMS320C30-40 (5 V)
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TMS320C30
SPRS032A
TMS320C30-50
40-ns
TMS320C30-40
50-ns
TMS320C30-33
60-ns
TMS320C30-27
74-ns
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16KX8
Abstract: TAG 106 D 64KX32 GS81132Q GSM31P256KB-I66 GSM31P512KB-I66 SRAM 16k*8
Text: GSM31P256KB-I66 GSM31P512KB-I66 GSI TECHNOLOGY GSM31P256KB-I66 GSM31P512KB-I66 256KB / 512KB Modules COASt 3.1 Specification Features Functional Description cont’d • • • • The GSM31P256KB-I66, and 256KB module, use GSI’s GS81132Q 32KX32 synchronous burst SRAM and a single
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GSM31P256KB-I66
GSM31P512KB-I66
256KB
512KB
GSM31P256KB-I66,
GS81132Q
32KX32
16KX8
TAG 106 D
64KX32
GSM31P256KB-I66
GSM31P512KB-I66
SRAM 16k*8
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Untitled
Abstract: No abstract text available
Text: SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS SGUS017H - OCTOBER 1993 - REVISED OCTOBER 2001 D D D D D D D D D D D D D SMJ: QML Processing to MIL-PRF-38535 SM: Standard Processing TMP: Commercial Level Processing TAB Operating Temperature Ranges: - Military M -55°C to 125°C
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SMJ320C40,
TMP320C40
SGUS017H
MIL-PRF-38535
C40-60:
33-ns
C40-50:
40-ns
C40-40:
50-ns
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05P8
Abstract: 8748
Text: SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS SGUS017H – OCTOBER 1993 – REVISED OCTOBER 2001 D D D D D D D D D D D D D SMJ: QML Processing to MIL–PRF–38535 SM: Standard Processing TMP: Commercial Level Processing TAB Operating Temperature Ranges:
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SMJ320C40,
TMP320C40
SGUS017H
C40-60:
33-ns
C40-50:
40-ns
C40-40:
50-ns
05P8
8748
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Untitled
Abstract: No abstract text available
Text: SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS SGUS017H - OCTOBER 1993 - REVISED OCTOBER 2001 D D D D D D D D D D D D D SMJ: QML Processing to MIL-PRF-38535 SM: Standard Processing TMP: Commercial Level Processing TAB Operating Temperature Ranges: - Military M -55°C to 125°C
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SMJ320C40,
TMP320C40
SGUS017H
MIL-PRF-38535
C40-60:
33-ns
C40-50:
40-ns
C40-40:
50-ns
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Untitled
Abstract: No abstract text available
Text: SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS SGUS017H - OCTOBER 1993 - REVISED OCTOBER 2001 D D D D D D D D D D D D D SMJ: QML Processing to MIL-PRF-38535 SM: Standard Processing TMP: Commercial Level Processing TAB Operating Temperature Ranges: - Military M -55°C to 125°C
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SMJ320C40,
TMP320C40
SGUS017H
MIL-PRF-38535
C40-60:
33-ns
C40-50:
40-ns
C40-40:
50-ns
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