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    CY7C141 Price and Stock

    Cypress Semiconductor CY7C1415KV18-250BZXC

    NO WARRANTY
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    DigiKey CY7C1415KV18-250BZXC Tray 1,649 1
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    Cypress Semiconductor CY7C1415KV18-250BZI

    NO WARRANTY
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    DigiKey CY7C1415KV18-250BZI Tray 625 1
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    Rochester Electronics CY7C1415KV18-250BZI 64 1
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    Flip Electronics CY7C1415KV18-250BZI 1,224
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    Cypress Semiconductor CY7C1414KV18-250BZXC

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    DigiKey CY7C1414KV18-250BZXC Tray 461 1
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    Cypress Semiconductor CY7C1418KV18-300BZXC

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    DigiKey CY7C1418KV18-300BZXC Tray 175 1
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    Rochester Electronics CY7C1418KV18-300BZXC 180 1
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    Flip Electronics CY7C1418KV18-300BZXC 2,477
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    Infineon Technologies AG CY7C1413KV18-250BZXC

    IC SRAM 36MBIT PAR 165FBGA
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    DigiKey CY7C1413KV18-250BZXC Tray 136 1
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    Mouser Electronics CY7C1413KV18-250BZXC
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    Arrow Electronics CY7C1413KV18-250BZXC 110 1
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    CY7C141 Datasheets (296)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CY7C141 Cypress Semiconductor 1K x 8 Dual-Port Static RAM Original PDF
    CY7C141 Cypress Semiconductor 1K x 8 Dual-Port Static Ram Original PDF
    CY7C1410AV18 Cypress Semiconductor 36-Mbit QDR-II SRAM 2-Word Burst Architecture Original PDF
    CY7C1410AV18-167BZXC Cypress Semiconductor 36-Mbit QDR-II SRAM 2-Word Burst Architecture Original PDF
    CY7C1410BV18 Cypress Semiconductor 36-Mbit QDR-II SRAM 2-Word Burst Architecture Original PDF
    CY7C1410JV18 Cypress Semiconductor 36-Mbit QDR-II SRAM 2-Word Burst Architecture Original PDF
    CY7C1410V18 Cypress Semiconductor 36-Mbit QDR-II SRAM 2-Word Burst Architecture Original PDF
    CY7C141-15JC Cypress Semiconductor 1K x 8 Dual-Port Static RAM Original PDF
    CY7C141-15JC Cypress Semiconductor 1K x 8 Dual-Port Static Ram Original PDF
    CY7C141-15NC Cypress Semiconductor 1K x 8 Dual-Port Static RAM Original PDF
    CY7C141-15NC Cypress Semiconductor 1K x 8 Dual-Port Static Ram Original PDF
    CY7C1411AV18 Cypress Semiconductor 36-Mbit QDR-II SRAM 4-Word Burst Architecture Original PDF
    CY7C1411AV18-167BZXC Cypress Semiconductor 36-Mbit QDR-II SRAM 4-Word Burst Architecture Original PDF
    CY7C1411BV18 Cypress Semiconductor 36-Mbit QDR-II SRAM 4-Word Burst Architecture Original PDF
    CY7C1411BV18 Cypress Semiconductor 36-Mbit QDR-II SRAM 4-Word Burst Architecture Original PDF
    CY7C1411BV18 Cypress Semiconductor 36-Mbit QDR-II SRAM 4-Word Burst Architecture Original PDF
    CY7C1411BV18-250BZC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 36MBIT 250MHZ 165FBGA Original PDF
    CY7C1411JV18 Cypress Semiconductor 36-Mbit QDR-II SRAM 4-Word Burst Architecture Original PDF
    CY7C1411KV18-250BZC Cypress Semiconductor Integrated Circuits (ICs) - Memory - IC SRAM 36M PARALLEL 165FBGA Original PDF
    CY7C1411KV18-250BZXC Cypress Semiconductor Integrated Circuits (ICs) - Memory - IC SRAM 36M PARALLEL 165FBGA Original PDF
    ...

    CY7C141 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    bzx 850

    Abstract: bzx 850 30
    Text: CY7C1412AV18 CY7C1414AV18 36 Mbit QDR II SRAM Two Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■ 2-word burst on all accesses


    Original     		PDF CY7C1412AV18 CY7C1414AV18 CY7C1412AV18, CY7C1414AV18 bzx 850 bzx 850 30

    Untitled

    Abstract: No abstract text available
    Text: CY7C1413JV18 CY7C1415JV18 36-Mbit QDR II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1413JV18 – 2M x 18 ■ 300-MHz clock for high bandwidth ■ 4-word burst for reducing address bus frequency


    Original     		PDF CY7C1413JV18 CY7C1415JV18 36-Mbit CY7C1413JV18 300-MHz

    CY7C1411BV18

    Abstract: CY7C1413BV18 CY7C1415BV18 CY7C1426BV18
    Text: CY7C1411BV18, CY7C1426BV18 CY7C1413BV18, CY7C1415BV18 36-Mbit QDR -II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth ■


    Original     		PDF CY7C1411BV18, CY7C1426BV18 CY7C1413BV18, CY7C1415BV18 36-Mbit CY7C1411BV18 CY7C1413BV18 CY7C1411BV18 CY7C1413BV18 CY7C1415BV18 CY7C1426BV18

    PLCC-52

    Abstract: CY7C130 CY7C131 CY7C140 CY7C141 CY7C131-25JC CY7C131-35J Z1014
    Text: CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 1K x 8 Dual-Port Static RAM Features Functional Description • True dual-ported memory cells, which allow simultaneous reads of the same memory location ■ 1K x 8 organization ■ 0.65 micron CMOS for optimum speed and power


    Original     		PDF CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 CY7C130/130A/CY7C131/131A/CY7C140 CY7C130/130A/ CY7C131/131A PLCC-52 CY7C130 CY7C131 CY7C140 CY7C141 CY7C131-25JC CY7C131-35J Z1014

    CY7C1416AV18

    Abstract: CY7C1418AV18 CY7C1420AV18 CY7C1427AV18
    Text: CY7C1416AV18 CY7C1427AV18 CY7C1418AV18 CY7C1420AV18 PRELIMINARY 36-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 36-Mbit density 4M x 8, 4M x 9, 2M x 18, 1M x 36 • 250-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency


    Original     		PDF CY7C1416AV18 CY7C1427AV18 CY7C1418AV18 CY7C1420AV18 36-Mbit 250-MHz CY7C1416AV18 CY7C1418AV18 CY7C1420AV18 CY7C1427AV18

    Untitled

    Abstract: No abstract text available
    Text: CY7C1411KV18/CY7C1426KV18 CY7C1413KV18/CY7C1415KV18 36-Mbit QDR II SRAM Four-Word Burst Architecture 36-Mbit QDR® II SRAM Four-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions


    Original     		PDF CY7C1411KV18/CY7C1426KV18 CY7C1413KV18/CY7C1415KV18 36-Mbit CY7C1411KV18 CY7C1413KV18 CY7C1415KV18

    Untitled

    Abstract: No abstract text available
    Text: THIS SPEC IS OBSOLETE Spec No: 001-12557 Spec Title: CY7C1413JV18/CY7C1415JV18, 36-MBIT QDR R II SRAM 4-WORD BURST ARCHITECTURE Sunset Owner: Jayasree Nayar (NJY) Replaced by: NONE CY7C1413JV18 CY7C1415JV18 36-Mbit QDR II SRAM 4-Word Burst Architecture


    Original     		PDF CY7C1413JV18/CY7C1415JV18, 36-MBIT CY7C1413JV18 CY7C1415JV18 300-MHz

    7C13135

    Abstract: CY7C140-35PC 7C130 CY7C130 CY7C131 CY7C140 CY7C141
    Text: CY7C130/CY7C131 CY7C140/CY7C141 1K x 8 Dual-Port Static RAM Features Functional Description • True Dual-Ported memory cells which allow simultaneous reads of the same memory location The CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K by 8 dual-port static RAMs. Two ports


    Original     		PDF CY7C130/CY7C131 CY7C140/CY7C141 CY7C130/CY7C131/CY7C140 CY7C141 CY7C130/ CY7C131 CY7C140/CY7C141 16-bit 7C13135 CY7C140-35PC 7C130 CY7C130 CY7C140

    78 ball fbga thermal resistance

    Abstract: No abstract text available
    Text: CY7C1411AV18 CY7C1413AV18 CY7C1415AV18 PRELIMINARY 36-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth


    Original     		PDF CY7C1411AV18 CY7C1413AV18 CY7C1415AV18 36-Mbit 300-MHz CY7C1426AV18 78 ball fbga thermal resistance

    Untitled

    Abstract: No abstract text available
    Text: CY7C14161KV18, CY7C14271KV18 CY7C14181KV18, CY7C14201KV18 36-Mbit DDR II SRAM 2-Word Burst Architecture Features Functional Description • 36-Mbit Density 4M x 8, 4M x 9, 2M x 18, 1M x 36 ■ 333 MHz Clock for High Bandwidth ■ 2-word Burst for reducing Address Bus Frequency


    Original     		PDF CY7C14161KV18, CY7C14271KV18 CY7C14181KV18, CY7C14201KV18 36-Mbit CY7C14271KV18, CY7C14201KV18

    CY7C1428AV18-250BZC

    Abstract: No abstract text available
    Text: CY7C1417AV18 CY7C1428AV18 CY7C1419AV18 CY7C1421AV18 36-Mbit DDR-II SRAM 4-Word Burst Architecture Features Functional Description • 36-Mbit density 4M x 8, 4M x 9, 2M x 18, 1M x 36 • 300-MHz clock for high bandwidth • 4-Word burst for reducing address bus frequency


    Original     		PDF CY7C1417AV18 CY7C1428AV18 CY7C1419AV18 CY7C1421AV18 36-Mbit 300-MHz CY7C1428AV18-250BZC

    Untitled

    Abstract: No abstract text available
    Text: CY7C1411KV18, CY7C1426KV18 CY7C1413KV18, CY7C1415KV18 36-Mbit QDR II SRAM 4-Word Burst Architecture 36-Mbit QDR® II SRAM 4-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions


    Original     		PDF 36-Mbit CY7C1411KV18, CY7C1426KV18 CY7C1413KV18, CY7C1415KV18 CY7C1411KV18 CY7C1426KV18 CY7C1413KV18

    CY7C1416BV18

    Abstract: CY7C1418BV18 CY7C1420BV18 CY7C1427BV18
    Text: CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18 PRELIMINARY 36-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 36-Mbit density 4M x 8, 4M x 9, 2M x 18, 1M x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency


    Original     		PDF CY7C1416BV18 CY7C1427BV18 CY7C1418BV18 CY7C1420BV18 36-Mbit 300-MHz enab1416BV18 CY7C1416BV18 CY7C1418BV18 CY7C1420BV18 CY7C1427BV18

    CY7C1411BV18

    Abstract: CY7C1413BV18 CY7C1415BV18 CY7C1426BV18
    Text: CY7C1411BV18, CY7C1426BV18 CY7C1413BV18, CY7C1415BV18 36-Mbit QDR -II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth ■


    Original     		PDF CY7C1411BV18, CY7C1426BV18 CY7C1413BV18, CY7C1415BV18 36-Mbit CY7C1411BV18 CY7C1413BV18 CY7C1411BV18 CY7C1413BV18 CY7C1415BV18 CY7C1426BV18

    Untitled

    Abstract: No abstract text available
    Text: CY7C1412AV18 CY7C1414AV18 36 Mbit QDR II SRAM Two Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■ 2-word burst on all accesses


    Original     		PDF CY7C1412AV18 CY7C1414AV18 CY7C1412AV18, CY7C1414AV18

    Untitled

    Abstract: No abstract text available
    Text: CY7C1418AV18 CY7C1420AV18 36 Mbit DDR II SRAM Two Word Burst Architecture Features Functional Description • 36 Mbit density 2M x 18, 1M x 36 ■ 300 MHz clock for high bandwidth ■ Two word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces 


    Original     		PDF CY7C1418AV18 CY7C1420AV18 CY7C1418AV18, CY7C1420AV18 CY7C1420AV18,

    Untitled

    Abstract: No abstract text available
    Text: CY7C1418BV18 CY7C1420BV18 36-Mbit DDR II SRAM 2-Word Burst Architecture Features Functional Description • 36-Mbit Density 2M x 18, 1M x 36 ■ 267 MHz Clock for high Bandwidth ■ 2-word Burst for reducing Address Bus Frequency ■ Double Data Rate (DDR) Interfaces 


    Original     		PDF CY7C1418BV18 CY7C1420BV18 36-Mbit CY7C1418BV18, CY7C1420BV18 CY7C1420BV18, 18-bit

    nec 2561

    Abstract: CY7C1410JV18 CY7C1412JV18 CY7C1414JV18 CY7C1425JV18
    Text: CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 36-Mbit QDR -II SRAM 2-Word Burst Architecture Features Configurations • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions CY7C1410JV18 – 4M x 8 ■ 267 MHz Clock for High Bandwidth


    Original     		PDF CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 36-Mbit CY7C1410JV18 CY7C1412JV18 nec 2561 CY7C1410JV18 CY7C1412JV18 CY7C1414JV18 CY7C1425JV18

    cy7c131-55nc

    Abstract: ZT12 CY7C130 CY7C131 CY7C140 CY7C141 IDT7130 IDT7140
    Text: CY7C130/CY7C131 CY7C140/CY7C141 W CYPRESS Features • 0.8-micron CMOS for optimum speed/power • Automatic power-down • TTL compatible • Capable o f withstanding greater than 2001V electrostatic discharge • Fully asynchronous operation • Master CY7C130/CY7C131 easily ex­


    OCR Scan     		PDF CY7C130/CY7C131 CY7C140/CY7C141 CY7C140/ CY7C141 CY7C130/ CY7C131; IDT7130 IDT7140 cy7c131-55nc ZT12 CY7C130 CY7C131 CY7C140 CY7C141 IDT7140

    ebe switches

    Abstract: CY7C130 CY7C131 CY7C140 CY7C141 7CJ41-25 7CI40-35
    Text: CYPRESS SEMICONDUCTOR 00 0 3 4 2 1 EbE D 5 • CY7C130/CY7C131 CY7C140/CY7C141 -Z Z A Z . o y n p rrQ C 1024 x 8 Dual-Port Static RAM SEMICONDUCTOR Features Functional Description • 0,8-micron CMOS for optimum speed/power • Automatic power-down • TTL-compatible


    OCR Scan     		PDF CY7C130/CY7C131 CY7C140/CY7C141 20O1V CY7C140/ CY7C141 CY7C130/ CY7C131; CY7C130/CY7C131/CY7C140/ ebe switches CY7C130 CY7C131 CY7C140 CY7C141 7CJ41-25 7CI40-35

    Untitled

    Abstract: No abstract text available
    Text: CY7C130/CY7C131 CY7C140/CY7C141 CYPRESS SEMICONDUCTOR Features Functional Description • 0.8-micron CMOS for optimum speed/power • Automatic power-down • TTL compatible • Capable of withstanding greater than 2001V electrostatic discharge • Fully asynchronous operation


    OCR Scan     		PDF CY7C130/CY7C131 CY7C140/CY7C141 CY7C130/CY7C131 CY7C140/ CY7C141 CY7C130/ CY7C131; CY7C130/CY 7C131/CY7C140/

    Untitled

    Abstract: No abstract text available
    Text: fax id: 5200 CY7C130/CY7C131 CY7C140/CY7C141 W CYPRESS 1K x 8 Dual-Port Static Ram Features Functional Description True Dual-Ported memory cells which allow simulta­ neous reads of the same memory location 1K x 8 organization 0.65-micron CMOS for optimum speed/power


    OCR Scan     		PDF 130/C 140/C 65-micron CY7C130/CY7C131 CY7C140/CY7C141 CY7C130/CY7C131; 48-pin CY7C130/140) 52-pin

    7C130

    Abstract: L1314
    Text: CY7C130/CY7C131 CY7C140/CY7C141 _ 1024 x 8 Dual-Port Static RAM aT ^ p -¿r CYPRESS ^ SEMICONDUCTOR E ach p o rt has independent control pins; chip enable C E , w rite enable (RyW), and output The CY 7C130/CY7C131/CY7C140/ enable (O E ). TVvo flags are p rovided on each


    OCR Scan     		PDF CY7C130/CY7C131 CY7C140/ CY7C141 CY7C130/ CY7C131; CY7C140/CY7C141 7C130/CY7C131/CY7C140/ CY7C14 7C130 L1314

    Untitled

    Abstract: No abstract text available
    Text: CY7C130/CY7C131 _ CY7C140/CY7C141 = SEMICONDUCTOR 1024 x 8 D ual-Port Static R A M Features Functional Description • 0.8-micron CMOS for optimum speed/power T he CY 7C 130/CY7C13 L/CY7C140/ CY7C141 arc high-speed C M O S IK by 8 dual-port static RA M s. Two ports are pro­


    OCR Scan     		PDF CY7C130/CY7C131 CY7C140/CY7C141 CY7C130/CY7CI31 CY7C140/ CY7C141 CY7C130/ CY7C131; CY7CI40/CY7C141 130/CY7C13 L/CY7C140/