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Rochester Electronics LLC CY7C1312CV18-250BZXC IC SRAM 18MBIT PAR 165FBGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CY7C1312CV18-250BZXC	Tray	1,879		9	1 - 10 $34.96 100 $34.96 1000 $34.96 10000 $34.96	Buy Now
Rochester Electronics LLC CY7C13121KV18-300BZXC IC SRAM 18MBIT PARALLEL 165FBGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CY7C13121KV18-300BZXC	Tray	1,586		8	1 - 10 $39.29 100 $39.29 1000 $39.29 10000 $39.29	Buy Now
Rochester Electronics LLC CY7C1312SV18-167BZC IC SRAM 18MBIT PAR 165FBGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CY7C1312SV18-167BZC	Tray	792		8	1 - 10 $39.94 100 $39.94 1000 $39.94 10000 $39.94	Buy Now
Rochester Electronics LLC CY7C1312CV18-167BZC IC SRAM 18MBIT PAR 165FBGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CY7C1312CV18-167BZC	Tray	717		10	1 - 10 $31.96 100 $31.96 1000 $31.96 10000 $31.96	Buy Now
Rochester Electronics LLC CY7C1312TV18-250BZC IC SRAM 18MBIT PAR 165FBGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CY7C1312TV18-250BZC	Bag	716		8	1 - 10 $39.94 100 $39.94 1000 $39.94 10000 $39.94	Buy Now

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CY7C1312 Datasheets (63)

Part	Manufacturer	Description	Datasheet Type	PDF
CY7C131-25JC	Cypress Semiconductor	1K x 8 Dual-Port Static Ram	Original	PDF
CY7C131-25JC	Cypress Semiconductor	1024 x 8 Dual-Port Static RAM	Scan	PDF
CY7C131-25JC	Cypress Semiconductor	Multiple Array MatriX High-Density EPLDs	Scan	PDF
CY7C131-25JC	Cypress Semiconductor	1K x 8 Dual-Port Static RAM	Scan	PDF
CY7C131-25JI	Cypress Semiconductor	1K x 8 Dual-Port Static Ram	Original	PDF
CY7C131-25JI	Cypress Semiconductor	1K x 8 Dual-Port Static RAM	Scan	PDF
CY7C131-25JXC	Cypress Semiconductor	1K x 8 Dual-Port Static RAM	Original	PDF
CY7C131-25JXC	Cypress Semiconductor	Memory, Integrated Circuits (ICs), IC SRAM 8KBIT 25NS 52PLCC	Original	PDF
CY7C131-25JXCT	Cypress Semiconductor	1K x 8 Dual-Port Static RAM	Original	PDF
CY7C131-25JXCT	Cypress Semiconductor	Memory, Integrated Circuits (ICs), IC SRAM 8KBIT 25NS 52PLCC	Original	PDF
CY7C131-25LC	Cypress Semiconductor	1024 x 8 Dual-Port Static RAM	Scan	PDF
CY7C131-25LC	Cypress Semiconductor	Multiple Array MatriX High-Density EPLDs	Scan	PDF
CY7C131-25NC	Cypress Semiconductor	1K x 8 Dual-Port Static Ram	Original	PDF
CY7C131-25NC	Cypress Semiconductor	1K x 8 Dual-Port Static RAM	Original	PDF

CY7C131-25NC	Cypress Semiconductor	1K x 8 Dual-Port Static RAM	Scan	PDF
CY7C131-25NI	Cypress Semiconductor	1K x 8 Dual-Port Static Ram	Original	PDF
CY7C131-25NI	Cypress Semiconductor	1K x 8 Dual-Port Static RAM	Scan	PDF
CY7C131-25NXC	Cypress Semiconductor	1K x 8 Dual-Port Static RAM	Original	PDF
CY7C131-25NXC	Cypress Semiconductor	Memory, Integrated Circuits (ICs), IC SRAM 8KBIT 25NS 52QFP	Original	PDF
CY7C131-25NXCT	Cypress Semiconductor	1K x 8 Dual-Port Static RAM	Original	PDF

CY7C1312 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
Untitled Abstract: No abstract text available Text: CY7C1312KV18, CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1312KV18 – 1 M x 18	Original	18-Mbit CY7C1312KV18, CY7C1314KV18 CY7C1312KV18	PDF
CY7C1310V18 Abstract: CY7C1312V18 CY7C1314V18 Text: 310V18 CY7C1310V18 CY7C1312V18 CY7C1314V18 ADVANCE INFORMATION 18-Mb 2-Word Burst SRAM with QDR -II Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 250 MHz Clock for High Bandwidth	Original	310V18 CY7C1310V18 CY7C1312V18 CY7C1314V18 18-Mb CY7C1310V18/CY7C1312V18/CY7C1314V18 CY7C1310V18 CY7C1312V18 CY7C1314V18	PDF
CY7C1310AV18 Abstract: CY7C1312AV18 CY7C1314AV18 Text: CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 PRELIMINARY 18-Mb QDR -II SRAM 2-Word Burst Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz clock for high bandwidth • 2-Word Burst on all accesses	Original	CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 18-Mb 167-MHz 167MHz CY7C1310AV18/CY7C1312AV18/CY7C1314AV18 CY7C1310AV18 CY7C1312AV18 CY7C1314AV18	PDF
CY7C1310BV18 Abstract: CY7C1312BV18 CY7C1314BV18 CY7C1910BV18 Text: CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit QDR -II SRAM 2 Word Burst Architecture Features Functional Description Separate Independent read and write data ports ❐ Supports concurrent transactions • 250 MHz clock for high bandwidth ■ 2 Word Burst on all accesses	Original	CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit CY7C1310BV18, CY7C1910BV18, CY7C1312BV18, CY7C1314BV18 CY7C1310BV18 CY7C1312BV18 CY7C1910BV18	PDF
Untitled Abstract: No abstract text available Text: CY7C1310KV18, CY7C1910KV18 CY7C1312KV18, CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1310KV18 – 2 M x 8 ■ 333 MHz clock for high bandwidth	Original	18-Mbit CY7C1310KV18, CY7C1910KV18 CY7C1312KV18, CY7C1314KV18 CY7C1310KV18 CY7C1910KV18 CY7C1312KV18	PDF
Untitled Abstract: No abstract text available Text: CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth	Original	CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit 250-MHz	PDF
Untitled Abstract: No abstract text available Text: CY7C1310KV18, CY7C1910KV18 CY7C1312KV18, CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions	Original	CY7C1310KV18, CY7C1910KV18 CY7C1312KV18, CY7C1314KV18 18-Mbit CY7C1310KV18 CY7C1312KV18	PDF
Untitled Abstract: No abstract text available Text: CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18 18 Mbit QDR -II SRAM 2-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1310JV18 – 2M x 8 CY7C1910JV18 – 2M x 9	Original	CY7C1310JV18, CY7C1910JV18 CY7C1312JV18, CY7C1314JV18 CY7C1310JV18 CY7C1312JV18	PDF
Untitled Abstract: No abstract text available Text: CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 PRELIMINARY 18-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth	Original	CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 18-Mbit 250-MHz	PDF
CY7C1312BV18 Abstract: CY7C1314BV18 CY7C1312 Text: CY7C1312BV18 CY7C1314BV18 18 Mbit QDR II SRAM Two Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■ 2-word burst on all accesses	Original	CY7C1312BV18 CY7C1314BV18 CY7C1312BV18 CY7C1314BV18 CY7C1312	PDF
Untitled Abstract: No abstract text available Text: CY7C1312KV18, CY7C1314KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Configurations Features Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1312KV18 – 1 M x 18	Original	CY7C1312KV18, CY7C1314KV18 18-Mbit CY7C1312KV18	PDF
Untitled Abstract: No abstract text available Text: CY7C1310V18 CY7C1312V18 CY7C1314V18 PRELIMINARY 18-Mb QDR -II SRAM 2-Word Burst Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz clock for high bandwidth • 2-Word Burst on all accesses	Original	CY7C1310V18 CY7C1312V18 CY7C1314V18 18-Mb 167-MHz 167MHz	PDF
CY7C1312BV18-167BZC Abstract: No abstract text available Text: CY7C1312BV18 CY7C1314BV18 18-Mbit QDR II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth	Original	CY7C1312BV18 CY7C1314BV18 18-Mbit CY7C1312BV18, CY7C1314BV18 CY7C1312BV18-167BZC	PDF
CY7C1310BV18 Abstract: CY7C1312BV18 CY7C1314BV18 CY7C1910BV18 Text: CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth	Original	CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit 250-MHz CY7C1310BV18 CY7C1312BV18 CY7C1314BV18 CY7C1910BV18	PDF

CY7C1310V18 Abstract: CY7C1312V18 CY7C1314V18 Text: CY7C1310V18 CY7C1312V18 CY7C1314V18 PRELIMINARY 18-Mb QDR -II SRAM Two-word Burst Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 167-MHz Clock for High Bandwidth • Two-word Burst on all accesses	Original	CY7C1310V18 CY7C1312V18 CY7C1314V18 18-Mb 167-MHz 167MHz CY7C1310V18/CY7C1312V18/CY7C1314V18 CY7C1310V18 CY7C1312V18 CY7C1314V18	PDF
CY7C1310BV18 Abstract: CY7C1312BV18 CY7C1314BV18 CY7C1910BV18 static SRAM single port Text: CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 PRELIMINARY 18-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports • Core VDD = 1.8V ±0.1V ; I/O VDDQ = 1.4V to VDD The CY7C1310BV18, CY7C1910BV18, CY7C1312BV18, and	Original	CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit CY7C1310BV18, CY7C1910BV18, CY7C1312BV18, CY7C1314BV18 CY7C1310BV18 CY7C1312BV18 CY7C1910BV18 static SRAM single port	PDF
Untitled Abstract: No abstract text available Text: CY7C13101KV18, CY7C13251KV18 CY7C13121KV18, CY7C13141KV18 18-Mbit QDR II SRAM 2-Word Burst Architecture 18-Mbit QDR® II SRAM 2-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions	Original	18-Mbit CY7C13101KV18, CY7C13251KV18 CY7C13121KV18, CY7C13141KV18 CY7C13101KV18 CY7C13251KV18 CY7C13121KV18	PDF
Untitled Abstract: No abstract text available Text: CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth	Original	CY7C1310BV18 CY7C1910BV18 CY7C1312BV18 CY7C1314BV18 18-Mbit 250-MHz	PDF
Untitled Abstract: No abstract text available Text: CY7C13101KV18, CY7C13251KV18 CY7C13121KV18, CY7C13141KV18 18-Mbit QDR II SRAM 2-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C13101KV18 – 2M x 8 ■ 333 MHz clock for high bandwidth	Original	18-Mbit CY7C13101KV18, CY7C13251KV18 CY7C13121KV18, CY7C13141KV18 CY7C13101KV18 CY7C13251KV18 CY7C13121KV18	PDF
CY7C1314CV18 Abstract: CY7C1310CV18 CY7C1312CV18 CY7C1910CV18 CY7C1314CV18-250BZXC Text: CY7C1310CV18, CY7C1910CV18 CY7C1312CV18, CY7C1314CV18 18-Mbit QDR -II SRAM 2-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■	Original	CY7C1310CV18, CY7C1910CV18 CY7C1312CV18, CY7C1314CV18 18-Mbit CY7C1310CV18 CY7C1312CV18 CY7C1314CV18 CY7C1310CV18 CY7C1312CV18 CY7C1910CV18 CY7C1314CV18-250BZXC	PDF
CY7C1310CV18 Abstract: CY7C1312CV18 CY7C1314CV18 CY7C1910CV18 Text: CY7C1310CV18, CY7C1910CV18 CY7C1312CV18, CY7C1314CV18 18-Mbit QDR -II SRAM 2-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■	Original	CY7C1310CV18, CY7C1910CV18 CY7C1312CV18, CY7C1314CV18 18-Mbit CY7C1310CV18 CY7C1312CV18 CY7C1310CV18 CY7C1312CV18 CY7C1314CV18 CY7C1910CV18	PDF
CY7C1312CV18 Abstract: CY7C1314CV18 Text: CY7C1312CV18 CY7C1314CV18 18-Mbit QDR II SRAM 2-Word Burst Architecture Features Configurations • Separate independent Read and Write Data Ports ❐ Supports concurrent transactions CY7C1312CV18 – 1M x 18 CY7C1314CV18 – 512K x 36 ■ 250 MHz Clock for High Bandwidth	Original	CY7C1312CV18 CY7C1314CV18 18-Mbit CY7C1312CV18 CY7C1314CV18	PDF
CY7C1310AV18 Abstract: CY7C1312AV18 CY7C1314AV18 Text: CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 PRELIMINARY 18-Mb QDR -II SRAM 2-Word Burst Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz clock for high bandwidth • 2-Word Burst on all accesses	Original	CY7C1310AV18 CY7C1312AV18 CY7C1314AV18 18-Mb 167-MHz 167MHz CY7C1310AV18/CY7C1312AV18/CY7C1314AV18 CY7C1310AV18 CY7C1312AV18 CY7C1314AV18	PDF
Untitled Abstract: No abstract text available Text: CY7C1312CV18 CY7C1314CV18 18-Mbit QDR II SRAM 2-Word Burst Architecture 18-Mbit QDR® II SRAM 2-Word Burst Architecture Features Configurations • Separate independent Read and Write Data Ports ❐ Supports concurrent transactions CY7C1312CV18 – 1M x 18	Original	CY7C1312CV18 CY7C1314CV18 18-Mbit CY7C1312CV18	PDF

CY7C1312 Search Results

CY7C1312 Price and Stock

Rochester Electronics LLC CY7C1312CV18-250BZXC

Rochester Electronics LLC CY7C13121KV18-300BZXC

Rochester Electronics LLC CY7C1312SV18-167BZC

Rochester Electronics LLC CY7C1312CV18-167BZC

Rochester Electronics LLC CY7C1312TV18-250BZC

CY7C1312 Datasheets (63)

CY7C1312 Datasheets Context Search

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CY7C1310V18

CY7C1310AV18

CY7C1310BV18

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CY7C1312BV18

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CY7C1312BV18-167BZC

CY7C1310BV18

CY7C1310V18

CY7C1310BV18

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CY7C1314CV18

CY7C1310CV18

CY7C1312CV18

CY7C1310AV18

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