CY7C1276V18 Search Results

CY7C1276V18 Datasheets (1)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
CY7C1276V18		Cypress Semiconductor	36-Mbit QDR-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)		Original	PDF

CY7C1276V18 Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
Untitled Abstract: No abstract text available Text: CY7C1276V18 CY7C1263V18 CY7C1265V18 PRELIMINARY 36-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300 MHz to 400 MHz clock for high bandwidth	Original	CY7C1276V18 CY7C1263V18 CY7C1265V18 36-Mbit CY7C1276V18/CY7C1263V18/CY7C1265V18 CY7C1256AV18	PDF
CY7C1263V18 Abstract: CY7C1261V18 CY7C1265V18 CY7C1276V18 Text: CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18 36-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features • Configurations With Read Cycle Latency of 2.5 cycles: Separate independent read and write data ports ❐ Supports concurrent transactions	Original	CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18 36-Mbit CY7C1261V18 CY7C1263V18 CY7C1263V18 CY7C1261V18 CY7C1265V18 CY7C1276V18	PDF
CY7C1263V18-400 Abstract: No abstract text available Text: CY7C1261V18 CY7C1276V18 CY7C1263V18 CY7C1265V18 36-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • Separate independent read and write data ports The CY7C1261V18, CY7C1276V18, CY7C1263V18, and CY7C1265V18 are 1.8V Synchronous Pipelined SRAMs,	Original	CY7C1261V18 CY7C1276V18 CY7C1263V18 CY7C1265V18 36-Mbit CY7C1263V18-400	PDF
CY7C1261V18 Abstract: CY7C1263V18 CY7C1265V18 CY7C1276V18 Text: CY7C1261V18 CY7C1276V18 CY7C1263V18 CY7C1265V18 36-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • Separate independent read and write data ports The CY7C1261V18, CY7C1276V18, CY7C1263V18, and CY7C1265V18 are 1.8V Synchronous Pipelined SRAMs,	Original	CY7C1261V18 CY7C1276V18 CY7C1263V18 CY7C1265V18 36-Mbit CY7C1261V18, CY7C1276V18, CY7C1263V18, CY7C1265V18 CY7C1261V18 CY7C1263V18 CY7C1276V18	PDF
CY7C1261V18 Abstract: CY7C1263V18 CY7C1265V18 CY7C1276V18 Text: CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18 36-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features • Configurations With Read Cycle Latency of 2.0 cycles: Separate independent read and write data ports ❐ Supports concurrent transactions	Original	CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18 36-Mbit CY7C1261V18 CY7C1263V18 CY7C1261V18 CY7C1263V18 CY7C1265V18 CY7C1276V18	PDF
Untitled Abstract: No abstract text available Text: CY7C1263V18 CY7C1265V18 PRELIMINARY 36-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300 MHz to 400 MHz clock for high bandwidth	Original	CY7C1263V18 CY7C1265V18 36-Mbit	PDF